These are probably questions shared not only by me, but also by many others interested in Cerebras.

I have spent more than a decade studying and working on test design, fault diagnosis, and yield improvement, including my doctoral studies and my career at several semiconductor companies. In this article, I want to draw on that experience to build scenarios and calculate a WSE yield model, using the WSE specifications and repair methods Cerebras has disclosed so far and the knowledge of testing, yield, and failure analysis I have accumulated in the industry.

Of course, the calculations and numbers in this article are results from assumptions and models I built using public information. They are not Cerebras’s actual yield, and the problem cases may not occur in practice. Applying the actual N5 process conditions and Cerebras’s undisclosed repair techniques and test methodologies could lead to conclusions that differ in many respects from the assumptions in this article. Even so, I wrote this article because I believe it can be a useful guide for general readers without a technical background on how to understand and approach the yield of this unprecedented wafer scale semiconductor chip, the first of its kind in the world.

Disclaimer

This article is for informational purposes and is not a recommendation to buy or sell any specific stock. The author may hold positions in the stocks mentioned, and those positions may change without notice. Readers are responsible for their own investment decisions.

1. Cerebras’s Wafer Scale Chip Can Tolerate Defects

Cerebras’s WSE-3 uses approximately 46,225 mm² of wafer area as a single processor. The small unit that performs computation within it is the PE(Processing Element). Each PE contains a CE (Compute Engine) for computation, Local SRAM for storing data, and a Fabric Router for sending and receiving data.^{[1] [3] [9]}

Each router connects to its neighbors to the north, south, east, and west. This connection is called a Link, and moving along one link to the next router is called a Hop. We call a structure that repeats these connections horizontally and vertically in a 2D mesh a NoC, Network on Chip. Cerebras is known to use this NoC structure.^[9]

Then what does it mean that this wafer scale chip can tolerate defects?

WSE-3 is reported to contain approximately 970,000 physical PEs. In other words, about 70,000 more PEs are built than the 900,000 required for shipment.

A design that builds more circuitry than needed is described as incorporating Redundancy, logic repair, or fault tolerance. Cerebras has adopted this structure. The idea is to bypass defects instead of discarding the chip when they occur.^[1] This structure is possible because AI computation uses many cores with identical functions, and defective cores can be replaced if spare cores and valid connections are available.

In fact, this is not a new concept. SRAM has long improved yield through memory repair, replacing defective cells with spare rows and columns. The same is true of the conventional GPUs we know. For example, H100 SXM physically contains 144 compute blocks called SMs (Streaming Multiprocessors). Two SMs form one TPC (Texture Processing Cluster), and only 66 of the 72 TPCs are actually used.^[4] In other words, GPUs already use a form of fault tolerance.

However, the two structures use different units for shipment qualification. GPUs are judged on whether each die passes, while WSE must secure all the required PEs and connections within a single wafer.

Subscribe now

2. Cerebras’s 100x Defect Tolerance Figure Is Really Just a Marketing Number

Cerebras claims that, at the same defect density, a wafer containing 72 dies comparable to H100 loses 361 mm² from about 59 defects, while one WSE-3 loses only 2.2 mm² from about 46 defects. It says this is a difference of 164 times, and that its resulting silicon utilization of 93% is higher than H100’s 91.7%.^[1]

Is that really true?

Of course, the numbers from the simple calculation are correct.

But they do not tell us how many wafers out of 100 actually pass. They do not represent actual yield.

To examine this from a yield perspective, I built a random defect model and ran the calculations.

I assumed that defects occur at independent locations and damage only the affected core. I omitted placement constraints within each GPC and defects in shared circuitry, following the same simplification used in Cerebras’s blog.

For the GPU, I used a Floorsweeping model that disables defective TPCs. I assumed a pass if the required 66 TPCs remained after excluding up to six of the 72, and also calculated a supplementary case in which SMs were excluded individually.

I divided WSE into 84 repair regions, allowed up to 833 defective PEs to be replaced per region, and allowed unrestricted connections within each region. 833 is an analytical assumption, not a disclosed actual repair limit.

Note: Both models judge pass or fail only by core count. This is not a comparison using actual yield data from TSMC’s 5 nm process.^{[4] [5]}

What yield does this defect model produce at D0 = 0.1, the value Cerebras used in its blog?

Regardless of the 164 times figure mentioned in the blog, the calculated results are 99.998% for the GPU TPC model and above 99.999% for the WSE model, which are almost the same. A die fails only if defects affect at least seven TPCs.

At an average of 0.81 defects per die, that occurs in about two out of 100,000 dies.

Next, I calculated the result at D0 = 0.4, four times 0.1, and found an average of 3.3 defects per GPU die. Even under the least favorable assumption, where two SMs are disabled together as a TPC, the GPU model’s pass rate was 96.02%.

If SMs are disabled individually, the rate still exceeds 99.99%. WSE has about 185 defects per wafer, or about 2.2 per region, still far below the limit, so its pass rate exceeds 99.999%.

In other words, the yield gap widened somewhat as D0 increased, but within the range compared, most GPUs also retained the cores required for shipment.

164 times compares the area disabled by defects. It does not mean that shipment yield or the number of defects that can be handled differs by a factor of 164.

Subscribe now

3. Not All Defects Occur in Locations That Are Easy to Repair

In my view, the hardest part of repair (whether for memory or logic) is that defects do not occur in the way I anticipated in the design, and this can make the repair method more complicated.

There are many possible defect cases, but one that I think makes repair difficult is the cluster defect model. Defects concentrated in one place may require repair and reconfiguration over a wider area.

To examine this, I tested a model that selects and connects 45 good PEs out of 63, referring to an example in Cerebras’s patent.^[2]

I placed seven defects in both A and B. In A, they were placed in one row. In B, some were placed in two consecutive rows within the same columns. In Figure 4, five good PEs are selected in each column to form a total of 45. A can be repaired with a 2p connection that skips one PE, but columns 4 and 5 of B require 3p connections because two consecutive defective PEs must be excluded. The physical locations of the PEs remain unchanged; only the connection settings change.

The performance impact of this difference needs to be considered separately for each bypass method. The dedicated bypass in this model is physical wiring that skips intermediate routers. With no additional pipeline stage in between, the signal must cross the long wire within one clock cycle. By contrast, packet rerouting through other good routers can reduce communication performance through additional hops and traffic contention. The delays of these two methods therefore cannot be calculated as if they were the same.^[2][9][12]

Applying a public wiring model and assumed circuit delays to the dedicated bypass, both A and B pass at 875 MHz. Both still pass under the baseline conditions when the target frequency is raised to 1.5 GHz. Under the worsened delay conditions, however, B’s minimum required clock period rises to 703 ps, exceeding the 667 ps limit. Of the two configurations that secured 45 good PEs, B succeeds in repairing the connections but still fails to meet the target frequency specification.^[11]

Subscribe now

4. Parametric Failures Can Further Worsen Cerebras’s Yield

As seen in Section 3, using a long bypass to route around cluster defects increases wire delay. If delay changes caused by process, voltage, and temperature (PVT) are added to this, the target clock specification may not be met. Then how does yield change if this performance variation differs by location within the wafer?

This time, I excluded the connection issues discussed earlier and analyzed only the effect of parametric failures related to PVT. Referring to spatial variation approaches in published research, I created three maps with slow regions at the center, in a ring, and at the edge. I kept the performance values and their area fractions identical across the circular wafer and changed only their locations.^{[15] [16] [17]} With voltage and temperature fixed, I expressed maximum operating frequency, Fmax, as a relative value with a mean of 100 and set the target to 92. I checked whether the required number of TPCs meeting the target frequency remained on each GPU die, and whether the required number of PEs remained on a single WSE wafer.

The difference in the two structures’ results comes from the unit at which regions below the performance requirement are excluded. If Fmax is low at the center, GPUs can exclude dies that fail the specification and ship the other dies. WSE must secure 900,000 PEs on the same wafer, so if spare PEs cannot replace a wide region below the performance requirement, that entire wafer falls short of the specification.

The figure shows the result for one wafer. Even with the same spatial distribution, the overall Fmax level can differ from wafer to wafer. When I applied this variation across multiple wafers, the WSE wafer pass rate was about 44%, while the average GPU die pass rate was about 86% in the scenario with a large center variation.

In this model without connection constraints, the value that determines whether WSE passes is not the average Fmax, but the Fmax of the 900,000th fastest PE. Even if average performance is high, the required PE count cannot be secured if this value is below the target. As the curves below show, raising the target frequency reduces the number of passing PEs and lowers the wafer pass rate.

For reference, these results are not always unfavorable to WSE. If the performance degradation is at the edge, it may overlap less with WSE’s actual footprint and favor WSE. If it forms a ring, it can affect many GPU dies and reduce the benefit of screening individual dies. Yield therefore depends not only on average performance, but also on the extent to which the region below the performance requirement overlaps the product area.

Subscribe now

5. Wafer Scale Chips Can Incur Higher Test Costs

Even High TR Coverage Can Miss a Slow Path

The transition delay fault model (TR) is a common fault model for at speed testing that examines timing margin. It is suitable for checking slow to fall and slow to rise faults at a specific node, but has limitations in checking the delay of a specific path. In this subsection, I directly implemented and measured a small PE circuit to examine these limitations of the TR model.

The example PE used in the experiment below consists of an 8 bit ADD/XOR unit and a router that selects one of the north, south, east, and west inputs. I injected stuck at faults (SA), which fix a node at a logic value, and transition delay faults (TR), and selected patterns through fault simulation that compares responses. As a result, eight SA patterns and 14 TR pattern pairs detected all 382 node faults in each model.

However, the result changed when I increased the gate delays in the same circuit by 12%. At a 450 ps interval, all existing TR patterns passed, but two patterns that activated the full carry path required 453.2 ps and failed. The patterns that detected node transition faults had not necessarily activated the slowest path.

Processing the Defect Map and Repair Settings for the Entire Wafer Takes Time

To calculate the repair and test burden across the entire wafer, I expanded the experiment to a 1,024×1,024 PE array, a scale similar to WSE-3’s approximately 970,000 PEs. Referring to the flow in Cerebras’s patent for recording defective PE coordinates, selecting a usable array, configuring repairs, and retesting, I built a mesh model that changes connections according to defect locations.^[1][2]

I grouped 32×32 PEs into one test region, creating 1,024 regions in total, and broadcast the same patterns to up to 64 regions. Responses are compared and stored for each PE, and detailed results are read from failed regions to determine repair locations.^[18] I used 64 serial channels at 50 MHz for result readout and repair configuration. I set the initial PE and default connection test time for a defect free wafer to 1, then calculated the additional time for defect readout, repair configuration, and testing modified connections. Differences caused by channel count are compared separately in the appendix.

For random defects, the test time required for repair increased as defects spread across more regions. With 46 defects, testing took about 4% longer than the initial test. When I increased the defect count to 1,024, detailed results had to be read from 665 regions and 2,041 repaired connections had to be tested. Defect readout added about 13% of the initial test time, repair configuration about 3%, and connection testing about 22%, increasing total time by about 38%. With 4,096 defects, the increase was about 63%. The common PE test patterns remained the same, but the amount of additional work changed with the defect map.

For cluster defects, repair outcomes differed even with similar additional test times. I arranged 1,024 defects in 2×2 or 4×4 groups and applied the same 8% increase in circuit delay to both. Both cases took about 23% longer than the initial test. However, the 3p connections bypassing the 2×2 groups passed the 450 ps specification, while the 5p connections required for the 4×4 groups failed at 460.4 ps. In the latter case, the configuration could not be used even after repair configuration and connection testing were completed.

For parametric failures, shortening the target period increased both the number of PEs to exclude and the amount of repair testing. On the same speed map, setting the target to 450 ps produced a passing configuration with 10 PEs excluded, taking about 4% longer than the initial test. At 443 ps, the number of PEs to exclude rose to 782. Total test time increased by about 24%, after which one repaired connection failed the timing test. Even after screening PEs that failed the speed requirement, an additional test was needed to determine whether the configuration connecting the remaining PEs met the target period.

In this model, even repairable defects required additional test time. This was because, after defects were found in the initial test, repair configuration and verification of the selected paths still had to be performed. With the same equipment and hourly rate, this additional time increases the cost of that test process. The test cost of a structure that repairs an entire wafer at PE granularity must therefore include not only initial defect detection, but also the cost of configuring and verifying each wafer’s repair configuration.

The fact that the selected repair configuration can fail even after additional testing can further increase test cost per good unit. If a wafer is rejected for a timing failure after repair, as in the cluster and parametric cases, the test time spent on that wafer is reflected in the cost per good unit along with the test time spent on passing wafers. This is why the number of good units recovered through repair must be considered together with the test time the repair process requires.

Subscribe now

6. These Problems Can Worsen with Turbo

Cerebras says it doubled Turbo’s compute performance and SRAM and fabric bandwidth by improving the power delivery and cooling structures of the same WSE-3 silicon.^{[19] [14]} It places power converters close to the wafer to reduce resistive losses along the path supplying large currents, delivering about twice the power at nearly the same voltage.^[23]

But as with all semiconductor design, there is no free lunch. A higher target frequency means less delay is allowed in PE internal circuits and repair connections. Even if improvements in power delivery and cooling reduce actual delay, PEs or long bypasses with insufficient delay reduction may fall short of the new specification. Also, excluding more PEs that fail the speed requirement can make repair paths longer, and a shorter timing limit may apply to those paths. This means the additional test costs analyzed in Section 5 could become more severe.

A Long Bypass That Previously Passed May Fail the Higher Speed Specification

The cluster defect case in Section 3 failed timing because of the long bypass, even after good PEs had been connected. This means a connection that was acceptable at a lower frequency may exceed the specification when the target period is shortened. With Turbo, the timing of an existing repair configuration can become a problem even without additional defective PEs.

Improving power delivery does not change the length of signal wires fabricated on the same silicon. We cannot assume that wire RC delay and mux delay improve at the same rate as the internal PE circuitry. Under a higher speed specification, even a wafer with enough spare PEs may therefore be rejected because of long repair connections. This is a case where the connection conditions seen in Section 3 limit the configurations that can pass for a higher speed product.

More PEs Failing the Speed Requirement Can Also Make Repair Connections Longer

When the spatial variation from Section 4 is added, the repair configuration itself changes. If raising the target frequency excludes several PEs together in a slow region, it can both reduce the number of usable PEs and increase the distance needed to bypass that region. Even if average performance improves, there are two possible reasons for failure: not securing enough PEs, or the connections between the secured PEs failing the higher speed specification.

This second problem becomes visible if we keep the delay map from Section 5 unchanged and shorten only the test interval. At 444 ps, a connection skipping three PEs passed at 372.4 ps. At 443 ps, one more PE failed the speed requirement, so four PEs had to be skipped. The new connection’s delay increased to 459.3 ps and it failed. The allowed time decreased by 1 ps, but the delay increased by about 87 ps as the selected connection changed.

Even at 443 ps, 99.925% of all PEs passed the speed test. There was headroom in PE count alone, yet the selected repair configuration failed. This example does not calculate Turbo’s actual frequency or yield. It shows that the PE arrangement left by speed screening can sharply increase connection delay. Yield at a higher speed specification is affected both by how many slow PEs are excluded and by which connections are then required.

A Wafer Can Fail the Higher Speed Specification Even After More Test Time Is Spent

The same changes also create an additional testing burden. The high fault coverage of conventional transition delay patterns seen in Section 5 does not by itself guarantee the delay of the long paths actually selected. To avoid missing repair paths with reduced margin at the higher speed specification, patterns must observe transitions along the long paths under the corresponding mux selection settings. If existing patterns do not adequately test these paths, they must be supplemented with transition or path delay patterns that incorporate timing information.^[21]

Even when patterns can be reused, repair configuration and result readout take time. In the same model, shortening the test interval from 450 ps to 443 ps increased the excluded PE count from 10 to 782, and the time to write repair settings from 10.2 μs to 321.3 μs. In this case, SA and TR patterns were neither regenerated nor reapplied. Parallel testing kept defective PE readout and connection test times almost unchanged, but the time to write repair settings sequentially increased because those settings were concentrated in a particular test region.

Total test time increased from 1.04 times to 1.24 times the initial test time, but the 443 ps configuration ultimately failed connection timing. At 442 ps, the time becomes shorter again because the selected repair rule’s connection span limit is exceeded and the process stops early. This is not an improvement in test efficiency. It is the result of being unable to proceed with repair configuration and subsequent testing. If repair attempts continue by searching for another configuration, more time is needed to retest the changed settings and paths. That repetition is not included in this calculation.

The point where Turbo’s mass production burden can increase is that fewer repair configurations may pass the higher speed specification, while the test time spent before determining a failure may increase. If timing failures reduce the number of wafers that can be shipped, there are fewer good wafers from which to recover manufacturing costs. The cost of wafers rejected after repair and testing is also reflected in manufacturing cost per good wafer. Raising operating frequency through better power delivery and securing enough repairable wafers at that frequency are separate mass production challenges.

Subscribe now

Conclusion - We Need to Look at Yield and Test Costs After Repair

In the models in this article, what changed whether WSE passed was not just the number of defects, but their locations, PE speeds, and repair connection delays. When the target frequency rises, as with Turbo, fewer repair configurations may pass, while the test time spent before determining a failure may increase.

Cerebras’s competitiveness in mass production should therefore be evaluated by the proportion of wafers that meet the target specification after repair and the repair and test cost per good wafer. The spare PE count and the 164 times area comparison alone cannot explain these two conditions.

References

Public Specifications, Patents, and Papers

1. Cerebras, 100x Defect Tolerance: How Cerebras Solved the Yield Problem · January 13, 2025. The company’s comparison assumptions include a PE area of about 0.05 mm², spare cores, a defect density of 0.1 defects/cm², and a layout of 72 GPUs. Page 4 of a separate WSE-3 white paper gives a core area of about 0.038 mm², so I did not treat 0.05 mm² as an exact measured floorplan value. The blog explains both the advantages of small cores and cases where clusters exceed repair limits.

2. Cerebras, US11328208B2: Processor element redundancy for accelerated deep learning · I referred to the testing, defect map, array configuration, optional retesting, and frequency, voltage, and current qualification in FIG. 33; repair connections and equal cycle latency in FIG. 34 and 35; and selective exclusion of good resources, counts per column, adjacent connection constraints, and balancing of power distribution in FIG. 38B. These are patent embodiments, not confirmed actual production algorithms or test coverage for WSE-3/Turbo.

3. Sean Lie, The Cerebras Wafer-Scale Architecture for Deep Learning, WSE-3 white paper · Pages 3 and 7 of the official white paper explicitly identifying WSE-3 as the subject. I confirmed the 84 die configuration in the text. The illustration on page 7 is labeled WSE-2, so I used its 12 columns and 7 rows only as a reference for conceptual diagrams and hypothetical grids. PE allocation per region and repair limits are separate analytical assumptions. I also referred to SRAM per PE, the router with five ports, communication with neighbors in one cycle, colors, lossless flow control, and compensation across reticle boundaries on pages 3, 7, and 8.

4. NVIDIA, NVIDIA Hopper Architecture In-Depth · March 22, 2022. I confirmed GH100’s area of 814 mm² and 144 SMs, H100 SXM’s 132 active SMs and 66 TPCs, and the TSMC 4N process. Pass rates under defects at SM/TPC granularity are calculated using this article’s hypothetical models.

5. NVIDIA, Virtualizing Hardware Processing Resources in a Processor, US20260023112A1 · Describes floorsweeping that disables defective circuitry through fuses or other means, screening by the number of good TPCs, and reassignment of logical indices. It is not treated as a disclosure of H100’s specific production test rules.

6. TSMC, 5nm D0 Trend, 2020 Technology Symposium presentation slide · An archived image of presentation material from August 2020. I read approximately 0.3 to 0.33 three quarters before N5 mass production and approximately 0.1 to 0.11 around the start of mass production from the curve. The dotted line is the forecast at that time. The forum poster’s interpretation was not used as data.

7. Intel, Q3 2024 earnings call Q&A · Pat Gelsinger’s answer to Timothy Arcuri’s question. Management directly explained that an 18A D0 below 0.4 was good at that development stage, but not yet at HVM yield levels and needed to fall further. Full transcript archived by TickerTrends.

8. TSMC, official 2020 Technology Symposium announcement · August 25, 2020. Official announcement confirming the start of N5 volume production in 2020 and improvements in defect density. It does not disclose current measured N5 D0.

9. Cerebras SDK, Wafer-Scale Engine Architecture · Fabric router and compute engine in each PE, connections to four neighbors, the 2D mesh, and transfer of a 32 bit wavelet in one cycle. Actual router delays at gate level are not disclosed.

10. Belli·De Sensi, Stencil Computations on Cerebras Wafer-Scale Engine · May 8, 2026. I used the 875 MHz nominal frequency in the WSE-3 experimental methodology as the baseline operating point. It is not interpreted as the guaranteed or maximum clock of all WSE-3 products.

11. OpenROAD, Correlating RC Values for PDKs · I used examples of RC per unit length extracted from ASAP7 designs and the stated units of kΩ/μm and pF/μm. M4, M6, and M8 values were adopted as comparison inputs, not substitutes for TSMC N5 characteristics.

12. Cerebras SDK GUI, Timeline: Wavelet Traces · Distinguishes the Delayed state, where multiple inputs contend for an output router, from Backpressure, where the receiver cannot accept data. This supports distinguishing physical timing of a link that operates in one cycle from actual waiting time for delivery. Cut bandwidth and rerouting results in the appendix are my own calculations.

13. Cerebras SDK, Data Structure Descriptors · CE transmit and receive queues, microthread resources, and restrictions on simultaneous use. This supports the point that actual execution requires resource allocation in addition to path capacity. Queue depth was not used as router internal buffer depth.

14. Cerebras, Ultrafast Frontier Inference: Cerebras Deep Dive at Hot Chips 2026 · August 25, 2026. Improvements in power delivery and cooling, approximately twice the power at nearly the same voltage, and the structure and replacement method for individual wafer modules. I did not infer shipment pass rates by frequency or speed screening policies from this presentation.

15. Yin·Chen·He·Li, Data Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation Alignment · VTS 2025, DOI 10.1109/VTS65138.2025.11022948. The preprint was released in August 2024. It analyzes Vmin of actual 16 nm automotive chips and separates variation between wafers and between regions. The main text uses a separate Fmax scenario informed by that decomposition approach.

16. Yin·Chen·Xu·He·Li, Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing · ITC 2025. Covers 415 chips at 5 nm, 124 silicon odometer inputs, and DC scan, AC scan, and MBIST Vmin. Cited as evidence of using spatial and circuit specific information in actual 5 nm devices. The measurements were not used as the mean or standard deviation of WSE Fmax.

17. Sarkar·Lowe·Vincent, Virtual Semiconductor Fabrication: Impact of Within-Wafer Variations on Yield and Performance · 2025 Winter Simulation Conference, a two page research summary. A Lam Research model of virtual 14 nm FinFET manufacturing and process variation. I referred to its comparison of center, edge, and donut spatial patterns. The functions in the main text that move locations while retaining the same distribution, and the Fmax amplitude, were defined separately by the author.

18. Siemens, No-compromise packetized test improves DFT efforts · January 30, 2025. Describes broadcasting patterns, expected values, and masks to repeated cores, comparison and result storage within each core, and independent shift and capture control. This is not a claim that Cerebras uses this solution.

19. Cerebras, Cerebras Unveils CS-4: Up to 30 Times Faster than GPU-based Solutions · Announced August 18, 2026. Specifies doubled compute performance and SRAM and fabric bandwidth for WSE-3 Turbo, and increased operating frequency from improved power delivery. It does not provide exact internal clock values or shipment yields by frequency.

20. Kleveland·Ferolito·Morrison·Scherer, Wafer-Scale Integration for AI: The Holy Grail? · Cerebras, 2025 Symposium on VLSI Technology and Circuits, JFS3-1. The abstract on printed page 50 of the official Advance Program specifies adoption of in system burn in and HTOL using heated coolant. This is not used to imply that the same HTOL test is applied to every shipped unit.

21. Synopsys, TestMAX ATPG · Distinguishes fault models including conventional transition, slack based transition, path delay, and hold time, as well as integration with STA and wire extraction tools. This supports general DFT capabilities, not Cerebras’s adoption of a particular tool.

22. Ron Press, Test Points are Trending · Siemens/Mentor Graphics, October 14, 2015. Describes the transition fault model targeting large delays, timing aware ATPG that considers actual paths, path shortening through observe test points, and path delay patterns.

23. Jean-Philippe Fricker, explanation of design changes after the CS-4 launch · Public explanation by Cerebras’s cofounder. Distinguishes the 54.5 V DC path, DC/DC conversion in the backpack, an approximately 0.5 mm power delivery path, about twice the current at nearly the same voltage, and improvements in component count and assembly structure. The 100 times comparison in delivery distance is against a conventional GPU board. Improvements in manufacturing cost and first pass yield are qualitative company claims without yield figures.

Appendix

This appendix collects structural explanations and calculations left out of the main text. The numbers below are also model results, not actual product measurements.

Interview: September 30, 2026 Pacific Time / October 1, 2026 Taiwan Time
Interview and editing: Damnang
Expert: Process Integration Engineer at Micron Taiwan

When people talk about Micron, attention usually goes to HBM performance, production volume, and when the next generation product will arrive. This time I wanted to hear a different story. What kinds of problems arise inside the Taiwan fabs that actually make the memory, and how do the people there solve them?

The expert I spoke with previously analyzed defects caused by equipment, materials, and fab environments at Samsung Foundry. He now works in process integration at Micron in Taiwan. Our conversation began with the manufacturing differences between conventional DRAM and HBM, then moved into materials analysis, inspection costs, experimentation, and documentation.

The Taiwan story could not be left out. What did colleagues who chose Micron over TSMC value? How did compensation news from Korean memory companies affect Micron employees in Taiwan? How does a fab owned by an American company actually operate in terms of language and day to day work? These are hard to see from product announcements or earnings releases alone.

The compensation discussion was heavier than I expected. The expert described employees reacting openly in large group settings and said dissatisfaction among younger employees was particularly strong.

The conversation moved beyond absolute salary levels and toward a broader question: how widely had frustration spread over how company performance should be shared with employees?

This article reorganizes roughly 59 minutes of conversation by topic and is not a verbatim transcript. The answers reflect the expert’s personal experience and views, not Micron’s official position. Comparisons with Samsung are based primarily on his experience at Samsung Foundry. Public developments after the interview, including news from October 7, are separated into a follow up reporting section and are also separated from Damnang’s interpretation.

Subscribe now

Read more

After that, as doubts grew over how fast CPO mass production would expand, attention gathered on NPO, which had been seen as merely an intermediate step before CPO.

The market’s question has also changed.

Now, rather than whether CPO comes, the interest is which comes first and who benefits in the meantime as CPO and NPO grow together, and for the optical test companies that drew attention together with CPO, the key is whether their growth can continue whichever path leads.

In two articles in April and May, I treated optical test as a key watch point of optical interconnect investment, and I keep that view no matter which of CPO and NPO comes first. That is because whether the optical interconnect is pluggable, NPO or CPO, optical test is a process it must go through.

This article first scores the watch points I presented in April, then examines what new test demand NPO creates and how it carries that demand while CPO is late. It then presents how much more testing scale-up CPO needs than scale-out CPO when it comes, which numbers show that timing first, and which companies benefit and when in this process.

I am confident that after reading this article, you will gain the overall flow of optics and investment insights from the perspective of CPO testing.

This article is for informational purposes and is not a recommendation to buy or sell any specific stock. Prices and multiples are based on September 30, 2026 closing prices (FormFactor’s one-year return and forward multiple are as of September 29). I may hold the stocks mentioned and my positions may change, and investment decisions and responsibility rest with the reader. NFA / DYOR.

1. April’s five watch points: how far have they come

Of the five watch points I presented in April, production schedules and equipment orders moved in the expected direction. TSMC announced its 2026 production plan for COUPE on substrate, and news of the full production of NVIDIA’s Spectrum-X Ethernet Photonics came out on August 14. Aehr’s second-half bookings were also $97.9 million, above the expected $60 million to $80 million.

In contrast, there was no acquisition of an optical test company by Advantest.

Open CPX 1.0, released on September 17, also only set the module’s structural, electrical, optical connection, thermal management and control requirements, and did not unify the test items and conditions of the preceding wafer and optical engine stages.

Subscribe now

2. CPO is late, and NPO comes first

Scale-out CPO has already entered mass production with NVIDIA’s Quantum-X and Spectrum-X Photonics, but a research report released in early June lowered the scale-out CPO shipment forecast through 2027 below the previous one and pushed the introduction of scale-up CPO to 2029.

The delay reasons the report cited were optical engine assembly yield, the difficulty of integrating optical components directly into switch and GPU packages, and cost, and all three stem from CPO’s structure of attaching the optical engine directly to the package.

When the optical engine is attached to the same package as the switch chip, repair after assembly is impossible, unlike pluggables where only the defective module can be pulled out and replaced, so the whole package can be lost because of a single optical engine. In a configuration that uses 18 optical engines together, like Quantum-X, even assuming each optical engine is good with 99% probability, the probability that all 18 are good is only about 83.5%, and if each is 98%, it falls to about 69.5%.

NPO avoids this risk by plugging the optical engine into a socket right next to the chip instead of putting it inside the chip package.

It is a form in which the optical module that used to plug into the front panel is moved next to the chip and the signal correction chip inside the module (DSP) is removed, so even if a defect occurs, only the optical engine needs to be pulled out and replaced, and the manufacturing and test equipment of pluggables can be used almost as is.

That is why it has emerged now as a realistic alternative for scale-up, before the supply chain can handle the mass production of CPO.

On September 17, Huawei unveiled a SuperPoD using Hi-ONE (7.2Tb/s), the first NPO optical engine to enter mass production, explaining that NPO is the most realistic choice given today’s supply chain maturity, and in the field too, first shipments of NPO for hyperscalers in 2027 and volume expansion in 2028 are being discussed.

NVIDIA’s scale-up roadmap follows the same flow.

The 2027 Rubin Ultra NVL576 connects copper inside the rack and optics only between racks. The official announcement presented CPO, but in the supply chain, it is said that an NPO configuration is also being prepared for maintainability and securing volume, while CPO is the priority.

In the 2028 Feynman generation, the NVLink8 CPO switch is on the roadmap, and even then systems can choose between copper and CPO NVLink.

So, as I have always argued, I see the introduction of scale-up CPO in 2028, but I expect ramp-up volume to increase in earnest after the second half of 2029.

Subscribe now

3. NPO also creates new test demand

I covered the basic structure of optical testing in Everything You Need to Know About CPO Testing, which I wrote in April, so if you want to study the details, I recommend reading that article.

While electrical testing contacts terminals with probes to send and receive signals, optical testing adds the alignment of a fiber with a core of about 9µm to a silicon waveguide about 0.5µm wide and the checking of operation across temperature, so it takes a long time.

A test point is called an insertion, and the process of applying temperature or electrical stress for a set time to screen out devices that would fail early is called burn-in.

Every path goes through PIC (a photonic integrated circuit that handles light) wafer test, laser burn-in and link bit error rate validation, but where and how much testing happens differs by structure.

The figure above shows, for each test item, in which structure the burden grows.

NPO implementations vary slightly by company, and this article compares test items with pluggable and CPO based on the socketed optical engine of Open CPX, whose specification came out in September.

In NPO, the share of optical engine test, electrical validation together with the host chip, socket contact test and temperature test grows, and in CPO, full wafer testing, final testing together with the switch chip and pre-assembly burn-in increase greatly.

Pluggables test the finished module to standard specifications and replace the whole module when a defect appears, but in NPO the optical engine itself is the unit of replacement, so the optical engine test before plugging into the socket takes that role.

Because there is no test equipment that handles signals of 400G and above cheaply, in mass production the chip handles electrical validation itself, so this demand goes to high-speed instruments in the development stage and to test boards and sockets in mass production.

Since the optical engine is pressed into a socket next to the chip, socket contact and board warpage must be checked separately, and because it sits right next to a chip that generates a lot of heat, one must also check whether it operates over a wide temperature range.

These tests grow with volume from 2027, when NPO mass production starts, so even if CPO is late, demand for optical engine test, host chip validation and socket test arises first in NPO.

Subscribe now

4. While CPO is late, NPO carries the demand

Read more

Go Damnang

Damnang Research now holds over a hundred essays and more than 400 reader questions. The archive keeps growing, which makes it harder to know where to start.

If you subscribed recently, the map is the fastest way in.

Subscribe now

How to use it

Open the "Start here" tab and pick how you read: as an investor or as an engineer.

You get three essays to start with. Investors begin with "Why HBM Is So Hard to Make" and "The Bottleneck Map." Engineers get the HBM essay plus "CPO, Fully Dissected."

Then use the search box or the Threads and Essays filters to find topics: CPO, glass substrates, EUV lithography, HBM, power and thermals. Series have a "view all parts" link so you can read them in sequence.

Just click the “Free only” tab to browse all the free articles. Around 30% of my articles are currently free to read, and I plan to keep it that way.

The "Ask Damnang" tab holds reader questions. There are 413, with 225 answered. Search the archive there. Full answers live on Substack, and each question links back here.

Interested in collaborating with me? Click the “Work with Damnang” button or visit research.damnang.com and tell me what you have in mind.

Work w/ Damnang

What I want to build with my Substack

Free subscribers

Even if you only read the free articles and the free sections of paid posts, I want you to walk away having learned something technical.

Paid subscribers

The paid articles go deeper into what is actually happening across the industry. You can also ask me questions directly, and through me, tap into a community of more than 1,000 people currently working across the industry.

Founding subscribers (Not confirmed yet)

I am thinking about offering datasets, forecasts, and industry models that traditional research firms have charged tens of thousands of dollars for, but at a fraction of the price.

I want to push the advantages of independent research as far as I can 😎

Have suggestions for my research or ideas for a business collaboration?

Feel free to reach out anytime at research@damnang.com!

Thank you!

The importance of HBM bandwidth is now familiar. But what has to change inside HBM to make each pin faster? I wanted to understand whether a faster logic process would be enough, whether more TSVs were needed, and how the DRAM stacked above the base die could keep up.

The expert I spoke with designs HBM interfaces at Micron. After working on high speed interface design at Samsung, he moved to Micron, where he now works on both sides of the HBM base die: the interface to the GPU and the interface to the DRAM core dies. Our conversation began with the circuits that transmit and receive signals, then moved into bandwidth and heat in future HBM generations, custom designs, and architectures that stack memory directly on top of a compute chip.

What stayed with me most was how my own question had changed by the end of the conversation. I began by asking what it would take to make HBM faster. As we went on, I became more interested in who would design each part of this increasingly complex memory, and who would capture the value.

I had assumed that bringing memory and logic closer together would naturally expand the role of memory companies. The expert pointed to another possibility. If customers take on more of the logic and interface design, memory companies could end up with a narrower design role even as stacking technology advances. The Q&A below preserves the explanations and followup questions that led me to that realization.

KEY TAKEAWAYS

1. Pin speed is also a problem inside the DRAM.

Distributing incoming high speed data across more internal paths running at lower speeds can ease the demands on DRAM. The cost is more TSVs, more routing, more area, and greater expense.

2.Future HBM makes both receiving and routing harder.

Higher pin speeds increase channel loss and make signals harder to distinguish. If DRAM speed remains unchanged, the design must also accommodate more parallel paths.

3.Fewer layers do not tell the whole capacity story.

Electrical loading, supply conditions, and each customer’s product configuration all matter. Requests for fewer layers do not, by themselves, mean that the need for taller stacks has disappeared.

4.Progress in 3D stacking does not guarantee design control.

Reducing external connections does not eliminate the need to reconcile the speeds of logic and DRAM. If customer specific TSV layouts also require changes to the core die, design reuse and staffing become additional concerns.

The questions and answers have been organized by topic from the original recording. Repetition and personal conversation have been removed; this is not a verbatim transcript. The context distinguishing the expert’s experience, information heard from others, and personal reasoning has been preserved. The answers do not represent the company’s official position. Explanations added beyond the interview are labeled “Editor’s note,” and the interviewer’s analysis is labeled “Damnang’s take.”

Generative AI assisted with editing and the creation of visual material.

1. HBM has two distinct interfaces

Damnang

Could you start by briefly introducing the work you do?

Expert

I design HBM at Micron, specifically the interfaces. An interface enables chips to exchange signals reliably. Our job is to transmit clean signals, receive them without errors, interpret the incoming analog signals as digital data, and pass that data into the chip.

I specialized in high speed interface design during my PhD and also worked on SSD interface design at Samsung. I later moved to Micron, where I now design HBM interfaces.

Read more

This piece does not outline an actionable “high-conviction” idea, but instead explores what is happening in the optics sector and the key trends to watch.

I partnered with with Aurelion Research on this piece to pair an engineering read of optics with investment research built on company work and conversations with management.

Aurelion Research is an independent publication founded by former analysts at institutional investment funds, covering overlooked small and mid-cap stocks, investment themes, and commodities. Their research draws on conversations with management teams, and they take no compensation from the companies they cover.

They also publish the Aurelion Index, a portfolio of their highest-conviction ideas that they buy themselves. Their focus on valuation and timing complements the technology direction this piece starts from.

Table of Contents

1. Damnang’s Take on Optics: The Road Ahead

2. Fabrinet: Optical Manufacturing
   2.1 The Business

   2.2 In Conversation with Management
   2.3 Our Take on Fabrinet

   2.4 Damnang’s Take

3. Ciena: Optical Networking

   3.1 The Business
   3.2 In Conversation with Management
   3.3 Our Take on Ciena

   3.4 Damnang’s Take

4. Our Final Thoughts

1. Damnang’s Take on Optics: The Road Ahead

When analyzing AI infrastructure, attention tends to go to GPU performance and to memory capacity and bandwidth. Adding compute alone does not make a larger system, though.

The resources have to exchange data, and as the system grows, the network that connects them has to grow with it. I focus on optics because AI is changing not only how fast connections must be but also how far they must reach.

This change appears both inside and outside the data center. Inside, larger AI clusters need high-speed optical products to tie them together, and outside, infrastructure spread across multiple facilities needs bandwidth to connect it.

As AI models grow, the compute they need has become hard to fit within a single data center’s power, space, and cooling, so scale-across links that connect multiple data centers as one system are increasing.

The reason this article analyzes Fabrinet and Ciena is to see the growth of the same industry through different business models. Companies across the optical supply chain all belong to the same ecosystem, but they earn money in different ways. Fabrinet manufactures, on contract, the optical technologies its customers choose, so I check whether its work on new technologies turns into new program wins, higher production volumes, a wider customer base, and better margins.

Ciena is an optical networking systems company for which cloud and AI data center connections have become major sources of demand, so I check whether its technical strengths turn into market share and pricing power and whether its supply chain is ready to turn growing orders into revenue. The two companies also do business with each other, yet from the same demand a manufacturer and a systems company can earn different profits. That is why this piece analyzes them together without grouping them into a single “optical beneficiary” category.

From an engineer’s perspective, I check whether technology turns into customer adoption and reliable volume production, and this piece adds Aurelion’s company analysis and conversations with management to examine the conditions under which optical demand turns into business results.

Summary: We came away from our work on both Fabrinet (FN) and Ciena (CIEN) with a positive view of the businesses and the opportunities ahead. That said, we are not adding either company to the Aurelion Index at this time. We explain our thinking throughout the piece and why both companies are on our shortlist.

2. Fabrinet: Optical Manufacturing

The first company we look at is Fabrinet, which operates on the manufacturing side of optics, producing complex optical components used in data centers and communications equipment. This is a very different business from Ciena, which sits on the networking side. We’ll get into Ciena later in the report.

2.1 The Business

Fabrinet is a contract manufacturer that specializes in optical and electronic products. It makes things like optical components, lasers, and sensors that are used in data centers and communications networks. The company focuses on products that are difficult to manufacture and require specialized expertise.

This has helped Fabrinet build long-term relationships with major technology companies, while maintaining strong margins and a solid net cash position.

Its customers include Lumentum, Infinera, Acacia, Cisco, Intel, and NeoPhotonics. NVIDIA has also become a growing customer.

Fabrinet is headquartered in Thailand and has manufacturing facilities across several locations, including the United States, China, Malaysia, and Thailand.

Fabrinet: Geographic Footprint

Investment Thesis

Fabrinet benefits from the growing demand for optical technology as AI and data centers expand. The company makes the hardware that helps move large amounts of data between GPUs, servers, and data centers.

One of the bigger opportunities is NVIDIA. Fabrinet makes optical products for NVIDIA, including high-speed transceivers. As AI systems grow larger and more connected, we expect demand for these products to increase.

At the same time, Fabrinet has been adding other large customers, making its business more diversified. This allows NVIDIA to grow as a customer without becoming an even bigger concentration risk for Fabrinet.

FN is also building direct relationships with large technology companies, including Amazon, Cisco, and Ciena. This gives the company more opportunities to grow while also reducing its reliance on a few customers.

Its communications business is also starting to recover after several weak years, creating another potential source of growth. Changes in U.S. trade policy could provide another benefit. At the same time, Fabrinet is expanding its production capacity and preparing for newer technologies such as co-packaged optics.

Ciena could be the next major growth driver.

Fabrinet’s expanded relationship with Ciena started ramping in early 2026, just as Ciena’s optical business began to accelerate. We expect this relationship to become increasingly important and believe Ciena could account for more than 10% of its revenue over the next few quarters.

AWS and Trainium

Fabrinet is also expanding into compute. Amazon became an 11% customer in FY2026, alongside Cisco at 20%, NVIDIA at 16%, and Nokia at 11%. This shows how much more diversified Fabrinet’s customer base has become.

We think much of this growth is tied to Amazon’s Trainium chips. Fabrinet has already added production lines to support the business, and we see further upside as Trainium expands and AWS develops more of its own optical hardware.

Growth Is Accelerating

Fabrinet has grown at 15% annually over the past decade, with growth accelerating to 36% in 2026 as AI and hyperscaler spending picks up.

The key question is whether this growth can continue beyond 2026.

For us, the main things to watch are the ramp of Ciena and AWS, continued growth with NVIDIA, and whether Fabrinet can keep winning new programs with large technology companies. If these relationships continue to scale, the current growth rate could prove more durable than the market expects.

Another concern is that gross and operating margins have stayed around 11–13% since 2022. Despite the strong AI-driven growth, Fabrinet has yet to see much operating leverage. This raises a question about how much of the revenue growth will actually flow through to earnings. If margins remain stuck in the same range, the upside from faster growth could be more limited than it first appears.

Methodology: Aurelion Research independently reaches out to company management teams and does not receive compensation from any companies covered. Interview responses are based on our notes and have been edited for clarity, so they may not reflect the speakers’ exact words. We selected the sections we found most relevant.

All information discussed is believed to be publicly available. This content is for informational purposes only and does not constitute investment advice or a recommendation to buy or sell any security.

2.2 In Conversation with Management

We recently had a conversation with Garo Toomajanian, Fabrinet’s VP of Investor Relations. Garo is an electrical engineer and previously covered semiconductors in equity research at a major bank, so he has a strong understanding of both the industry and the technology.

We started by asking why Fabrinet’s share price has come down so much recently. He pointed to FN’s historical exposure to communications, while noting that the company is expanding into other areas where its manufacturing expertise can be valuable. In his view, the opportunity is to focus on a few complex areas where Fabrinet can build an edge rather than trying to do everything.

He also highlighted the strength of Fabrinet’s customer relationships, which tend to be long-term and difficult to replace. From his perspective, the recent pressure is more related to costs and pricing than a fundamental change in the business.

So they clearly want to avoid staying too focused on an “old business segment” like communications, but they will need to prove it before the market trusts them and sees a clear path to more growth and less risk.

Customer Diversification

NVIDIA has been Fabrinet’s largest customer in recent years, but like we mentioned earlier, the mix is changing as the company builds more direct relationships with hyperscalers and other large technology companies.

Management was clear that it wants to avoid becoming too dependent on any single customer, while still seeing significant room to grow with NVIDIA.

FN is now getting new big customers like Amazon, Cisco, and Lumentum, but it is still reliant on a few large customers. This gives it a relatively sticky business as a manufacturer for the “big guys.” Management also pointed out that FN has the advantage of waiting for customers to decide what they want produced, without having to spend heavily on products that may never get produced.

At the same time, we think this means FN is still dependent on its customers placing orders, which gives the company less control over its own growth.

Another thing that stood out in the conversation was how early Fabrinet has been in some of the newer optical technologies. The company invested in silicon photonics roughly a decade ago and is now working on co-packaged optics.

We also asked him where he thinks we are in the broader optical cycle.

He did not want to say too much here. While the tone was optimistic, he did not seem as confident as we expected. That stood out to us, especially given how strong the AI and data-center demand story has been. This somewhat confirms what we thought: there is still uncertainty around how strong and long-lasting the optical cycle will be, which may be one reason investors have stayed away.

2.3 Our Take on Fabrinet

There are plenty of things that could happen with Fabrinet over the next few years. But when we step back, the story seems fairly simple: it looks like an undervalued company in a growing optical market.

At 21.9x NTM P/E, the valuation is reasonable, but we want to see better margins and more evidence of sustained earnings growth before getting more confident. For now, we think it makes sense to wait and see how these opportunities develop.

We also know Fabrinet is unlikely to get the same excitement or valuation as memory stocks like SK Hynix or SanDisk. Optics are becoming more important, but Fabrinet is still a manufacturing business, which also plays a role in how the market values the company.

For us, the key question is how much of today’s interest will turn into new programs, larger customers, and higher production volumes. We still do not have a clear answer, even after speaking with two of the largest optics companies in the world and doing our own work on the industry. We will have to wait for the next few quarters to get a better sense as these opportunities start to ramp.

2.4 Damnang’s Take

Fabrinet’s investment case examined above comes down to a wider customer base, rising optical demand, and readiness for new technology.

The technical question is how these opportunities connect to the company’s manufacturing capability. We should look separately at its ability to produce existing products reliably, maintain profitability, and secure a manufacturing role in the next generation of products.

Why Fabrinet’s Customer Relationships Last

The optical modules Fabrinet builds are finished only after fiber and optical components are aligned to within a fraction of a micron, and the assembled module’s optical performance is verified. A coherent pluggable for DCI, which links data centers, also has to fit a tunable laser, a modulator and receiver, and a DSP that processes the signal into one module, which makes the manufacturing process far more complex.

For products like these, the production process itself goes through customer qualification, so switching manufacturers means re-checking performance and reliability on the new process and stabilizing yield again.

That makes optical manufacturing a business in which customers cannot easily change manufacturers, and I think this gives Fabrinet, whose processes have already passed qualification with many customers, a technical moat.

Manufacturing Strength and Pricing Power Are Different

Making hard-to-make products well does not bring pricing power by itself, however. Bargaining power instead tends to arise at the supplier of a key component when that component is scarce. The laser, which I have emphasized many times in my articles, is exactly that kind of component.

So when looking at Fabrinet, a larger share of high-speed products should not be read as a structure in which margins automatically rise; what matters is how much margin it can capture from the extra alignment, assembly, and test work in new programs and from fewer defects as production stabilizes.

Fabrinet’s Role in NPO and CPO Manufacturing

Optics is also moving toward the chip in two forms:

(1) Near-packaged optics (NPO), which puts the optical engine as a separate module on the board right next to the chip, and (2) co-packaged optics (CPO), which puts it inside the same package as the switch chip.

Rather than going straight to CPO, which is harder to test and produce in volume, the industry is trying to use NPO as much as possible, and I think the current direction gives Fabrinet a bigger opportunity. That is because an NPO engine is built and tested on its own before it goes onto the board, which is closer to the module factory model Fabrinet does well.

In particular, as engines scale to 6.4T and 12.8T, I expect the ability to handle the rising manufacturing complexity and secure yield to become a technical advantage for FN. In short, I think the longer the NPO period lasts, the better the structure is for Fabrinet.

In CPO, by contrast, the optical engine is packaged together with the switch chip on a semiconductor packaging line, and the lasers move out to separate external laser source (ELS) modules, so the assembly, alignment, and testing a module factory did in one place are split among several companies.

NVIDIA listed Foxconn and Fabrinet in a 2025 technical blog as assembly and test partners for its CPO switches, but Fabrinet was not in the manufacturing chain for the 2026 production switch shown below.

The figure shows one NVIDIA design, and Fabrinet says it is already building CPO devices for a handful of customers, although not yet at full-scale volumes.

So I do not read one list as Fabrinet being pushed out of CPO for now, but it is clear that Fabrinet also needs to prepare for the CPO era. In CPO, the steps closest to the module factory work Fabrinet has done are ELS module assembly, engine testing before packaging, and fiber attach.

What Fabrinet needs now is likely wafer-level packaging, the process needed to make the optical engine itself, which builds wiring and connection points onto chips before they are cut from the wafer. This is a semiconductor process different from what module factories have done. To fill this gap, Fabrinet bought about a 14% stake in Raytek Semiconductor, a Taiwanese wafer-level packaging company, for about $32M in April 2026, and has said it plans to put this process in place in Thailand in its own lines or together with Raytek.

Fabrinet’s Manufacturing Role in Scale-Across

Scale-across routes have started to see the first orders for multi-rail systems, which lay many fiber pairs along one route. A multi-rail system packages and manages those fiber pairs as one optical system, so each deployment needs more assembly steps. Fabrinet names the dense fiber routing, fusion splicing, which joins fiber ends by melting them together, and connectorization these systems need as its strengths, and is working with several customers on multi-rail programs. This is the new work scale-across creates for Fabrinet.

In the end, I think Fabrinet’s next step depends on turning new manufacturing roles in NPO, CPO, and scale-across into real volume. It will be necessary to confirm which steps Fabrinet handles in NPO, CPO, and ELS production programs, whether multi-rail programs show up in revenue, and whether that work turns into profit.

3. Ciena: Optical Networking

The second one we look at is Ciena, which operates on the networking side of optics, building the systems that move massive amounts of data across fiber networks.

3.1 The Business

Ciena helps companies move large amounts of data through fiber-optic networks. Its equipment is used by telecom companies, cloud providers, and large businesses to connect data centers and cities.

Ciena is one of the major players in optical networking and competes with companies such as Nokia, Huawei, and Cisco. It is also expanding its presence in data centers as cloud and AI demand grows.

Investment Thesis:

We see AI as one of the main drivers of increasing demand for Ciena’s products as data centers become more connected. As computing continues to grow faster than many expect, more data will need to move between locations, driving demand for faster and higher-capacity networks.

Global Presence: Ciena has manufacturing and supply chain operations across North America and Asia, giving it the ability to support customers worldwide.

Ciena: Geographic Footprint

Revenue & Growth Outlook

Management expects Ciena to grow revenue at 30% annually from 2026 to 2029. That is a big target, especially after the recent acceleration.

The other part of the story is margins: Ciena is targeting a 50% adjusted gross margin and a 20% free cash flow margin by 2029. If both growth and margins move in that direction, the earnings and cash flow growth could be substantial.

Over 50% of Ciena’s revenue now comes from direct cloud customers. The rest is spread across service providers, cable companies, and government customers, giving it exposure to several different sources of networking demand.

Ciena has a strong position in optical line systems. The company has continued to gain share in this market, supported by its product roadmap and execution.

At the same time, Ciena has continued to grow revenue while gaining market share, which says a lot about the strength of its position in the market.

3.2 In Conversation with Management

We recently had a conversation with Gregg Lampf, Ciena’s VP of Investor Relations. Management expects data centers to become a larger part of Ciena’s business as AI infrastructure expands.

For us, the more interesting part is what this could do to the quality of Ciena’s revenue. Data-center customers typically require much higher-capacity equipment and are investing heavily in network upgrades. If the company is able to capture more of this spending, which management believes it will, we see this as something that could shift the business toward larger, higher-value programs rather than simply adding more volume to its existing customer base.

Our conversation also changed how we think about Ciena.

Even if we know it is no longer just a traditional telecom equipment maker, part of the market still seems to see it that way. If we, as generalists, are starting to see Ciena differently, maybe the rest of the market will too.

If Ciena is increasingly seen as an optical infrastructure company tied to the future of AI and data centers, we think this could help the growth story.

TAM & Market Share

We asked about Ciena’s TAM and market share.

No surprise here, since it is already in their presentation: management sees its addressable market nearly doubling from $27B today to $52B by 2029, with much of that expansion coming from new data-center opportunities.

What caught our attention is that Ciena has consistently gained market share in a fragmented and competitive market. Management credits its product roadmap and execution. If Ciena can keep taking share as the market expands, the upside could be much greater than simply growing with the market.

Supply Chain

Ciena recently appointed a new supply chain leader who reports directly to the CEO. They expect this to help the company handle higher demand and growing data-center volumes. We think it’s a smart and needed move, but Ciena is still relatively small within the broader optical supply chain. They will need to scale and move into larger, more demanding programs. Having the demand is one thing, but securing the components and capacity to deliver on time is another.

What About Pricing?

That’s one of our concerns, so we asked them about it.

Ciena has been raising prices since last year and continues to push for higher pricing with customers. Contract terms have also become less flexible, with no return or refund provisions. This suggests Ciena has some pricing power, which is encouraging, but we still need to see how long demand can stay this strong.

For now, demand is there, but Ciena was not very specific on how long it expects this to continue, even though we would have liked more clarity here.

3.3 Our Take on Ciena

Overall, we see Ciena as the more interesting setup of the two in the near term, with more direct exposure to the AI buildout and continued market share gains. That said, the main issue here is valuation.

At 35.7x NTM P/E, the market is already giving Ciena a lot of credit for the growth ahead. We like the direction of the business, but we would rather wait for either a better entry point or more evidence that the growth can continue.

3.4 Damnang’s Take

When I look at Ciena as an AI infrastructure company, I think what matters more than the share of revenue from cloud customers is how Ciena’s products and technology solve the technical limits customers run into as they connect more data centers. When that technology lowers a customer’s actual investment burden, the share gains and pricing power shown above will have a lasting basis.

Modems: Carrying More Data on One Fiber

Links between data centers carry data on a single fiber by splitting it across several colors of light, or wavelengths. Ciena’s core technology is WaveLogic, the coherent modem that puts data onto this light and reads it back.

The latest WaveLogic 6 Extreme carries 1.6T on a single wavelength, while the current products from competitors Cisco (Acacia) and Nokia are in the 1.2T class.

The more data the same fiber can carry, the less equipment and power customers need. Even when a hyperscaler designs its own equipment, Ciena has won a deal to supply WaveLogic 6 as a module. Competitors’ 1.6T products are due around 2027, though, so I see the modem lead as roughly one generation.

Line Systems: Letting Customers Use More Fiber

Because one fiber can only carry so much, capacity between data centers ultimately grows by using more fiber. Over long distances, weakened light has to be boosted at amplifier huts roughly every 80 km, and once fiber counts reach the hundreds, the huts run out of space and power first.

Ciena’s Hyper-Rail is a line system that raises the number of fiber pairs one rack can amplify from 4 to as many as 128. In Ciena’s example of a 20 Pb/s route, the number of huts needed at each amplifier site falls from 22 to one.

Amplifiers boost light using energy from pump lasers, so more fiber also means more pump lasers. This is the background to Ciena naming pump lasers first among its supply constraints and signing supply agreements through 2029.

Cisco and Nokia have announced similar multi-rail products, and Nokia cites 160 pairs per rack, but Ciena is the one that co-designed its system with hyperscalers and won the industry’s first order.

Extending Into Data Centers

The inside of the data center is a new market for Ciena. Ciena expects coherent technology to be used inside data centers from the 3.2T generation, and through the Nubis acquisition, it gained Nitro, a chip that boosts signals in copper cables inside the rack, and Vesta, a 6.4T CPO optical engine. Vesta has sample orders, with revenue expected from 2027. Competition in this market is only starting, so the point of judgment will come when customers actually adopt these products.

Technical Edge and Moat

In short, I think Ciena’s technical edge is clearest in modems and line systems for long-distance, high-capacity links. The modem gap narrows with each generation, and competitors are catching up on, or even exceeding, line system density. However, a route often runs on one company’s line system, and as shown above, Ciena has the largest installed base in this market.

So I see Ciena’s moat less in individual product specifications than in getting into cloud customers’ routes first as the standard. Whether hyperscalers standardize on Hyper-Rail by the end of 2026 will be the test.

4. Our Final Thoughts

There is no doubt that optics is becoming an increasingly important part of AI infrastructure as more data needs to move between chips, servers, and data centers. Fabrinet and Ciena give us two different ways to play this trend.

Fabrinet is focused on manufacturing the optical hardware, while Ciena builds the networks that move the data. Both are benefiting from growing demand and increasing investment across the data center ecosystem.

After speaking with both IR teams, we came away impressed by both businesses and think the opportunity in optics is still in its early stages. However, we still don’t have enough visibility on how quickly demand will translate into sustained growth, so we are not ready to take a position yet.

Valuation is the main reason. Ciena trades at around 35.7x NTM P/E, while Fabrinet is cheaper at 21.9x, but both still look quite expensive to us.

The other issue is timing. We like both companies, but we need more visibility on how the market will value their changing growth profiles. For now, we’ll wait for a clearer setup before adding either to the Index and continue to follow the optical cycle closely.

We’ll continue to follow these companies closely as the industry evolves.

Damnang and Aurelion Research

Disclosures & Methodology

All forecasts and estimates are based on publicly available information, management commentary, and our own modeling assumptions. This report reflects independent analysis by Aurelion Research and/or Damnang Research. All opinions and estimates expressed herein reflect the author’s judgment as of the date of publication and are subject to change without notice. This publication is for informational and educational purposes only and does not constitute investment advice, a solicitation, or a recommendation to buy or sell any security. Aurelion Research, Damnang Research, and its analysts may or may not hold positions in securities discussed. Use only where legally permitted.

With experience spanning equipment, process development, and R&D, he brings a broad perspective across the packaging stack and shared a number of practical insights throughout this discussion.

The Starting Question

If HBM stacks move to eight or even four layers, will that delay the adoption of hybrid bonding? This was one of the questions I wanted to explore in this expert call.

In this conversation, we discussed hybrid bonding technology from several angles, with a particular focus on HBM.

We covered when hybrid bonding is likely to be adopted in HBM, what is currently holding back the transition, what needs to change in terms of process equipment, how large the current technology gap is between Samsung and SK hynix in HBM hybrid bonding, and why Besi has become one of the most closely watched hybrid bonding equipment suppliers.

The expert views 2026 to 2030 as a key transition period for HBM hybrid bonding and believes it will ultimately become an essential technology. We go through the technical details and practical challenges behind that transition in the report below.

Key Takeaways

1. The number of layers alone does not determine the need for hybrid bonding.

   The expert identified height and thermal performance as the main drivers for HBM today, while describing a separate adoption condition for products that require finer pitch.

2. Maturity in bonding a single layer is not the same as readiness to produce multilayer stacks.

   Beyond the economics of the existing process, the expert highlighted the challenge of maintaining quality across a combination of process steps.

3. Running one tool well and bringing multiple tools into consistent operation are different tasks.

   In addition to managing contamination during repeated operation, engineers have to identify and resolve differences between the tools they install.

4. Besi’s strength lies in improvements accumulated through actual production experience.

   The expert distinguished that experience in logic bonding from the final equipment selection for multilayer HBM.

5. Current challenges should be considered alongside the longer term transition.

   The expert personally sees 2026 to 2030 as an important transition period and described improvements to existing TCB processes and preparation for hybrid bonding as parallel efforts.

Editorial Note

The questions and answers have been organized by topic from the original transcript. “Damnang’s Commentary” presents the editor’s interpretation of the interview. The expert’s explanations and outlook reflect his personal views at the time of the conversation, not the company’s official position. Generative AI assisted with language editing and organization.

Read more

I plan to publish more institutional style expert call reports like this regularly on my Substack. I hope you will continue to follow and support my work.

Note: After organizing the content, I asked AI to help summarize and edit it. Please note that some signs of AI assistance may be present in the writing.

Subscribe now

Interview Overview

This conversation examined the benefits Intel’s process improvements can offer customers and the technologies needed to address power and memory challenges in AI systems.

Drawing on my experience in foundry design and memory research, I asked about the conditions for applying these technologies. The expert described research he had conducted and system configurations he had evaluated. The discussion moves from how the technologies work to customer choices, the value of memory capacity, and foundry competitiveness.

Expert Background

The expert is a researcher in Intel’s Technology Research organization.

After working in DTCO (Design Technology Co-Optimization), jointly optimizing memory devices, circuits and layouts, he now studies server power delivery and memory configurations from an STCO (System Technology Co-Optimization) perspective.

Depending on the technology, the organization conducts research looking approximately 3 to 15 years ahead.

Customer contracts and the commercial terms of individual businesses are outside the scope of his direct work.

Key Discussion Points

• Improvements to routing and power delivery paths in 18A and 14A should be assessed against customers’ performance, power consumption and thermal requirements.

• System research considers losses in both power delivery and data movement. Integrating GaN with silicon is one research direction for improving power delivery.

• Changes in HBM stack height need to be considered alongside total capacity, space for connections and communication latency. The discussion compares Damnang’s software efficiency hypothesis with the expert’s inference example.

• The discussion examines the ability to offer design experience, process technology and packaging together, and the conditions needed to turn those capabilities into customer use and business results.

Editorial Note

Damnang’s and the expert’s remarks are identified by speaker. Commentary presents editorial interpretations of the business and investment implications, based on the discussion. The expert’s name and material discussed on a private basis have been omitted.

Views and expectations reflect each speaker’s judgment at the time of the interview. The final additional comment was included at the expert’s request.

1. How 18A and 14A Change Customer Chip Design

Damnang

What has changed most with 18A compared with previous processes?

Read more

However, now in 2026, this trend is changing. There are reports from the industry that NVIDIA has lowered HBM per GPU in Rubin Ultra from 288GB to 192GB and is preparing 8 layers as the new standard. This is quite different from the structure of 16 layers or more that the industry expected a year ago. I have also been covering this HBM density peak while meeting experts working in the memory industry over the past two months.

This is what I ultimately want to address in this article.

Will a memory downcycle really begin in 2028?

Based on the technical details and conversations with people working in the industry, I analyzed how the trend toward fewer HBM layers and the situation in 2028, when supply expansion is planned, would affect the memory cycle from a structural perspective.

In particular, I divided this into two scenarios, HBM with 8 layers and 4 layers, examined the memory hierarchy that HBM despec would affect, and used calculations based on this to predict how a memory downcycle might actually develop in 2028.

Disclaimer

This article is for informational purposes and is not an investment recommendation. Its scope is DRAM (HBM and general purpose DRAM), and it does not cover NAND. The information was checked as of September 14, 2026. The author may hold the stocks mentioned or change positions. Investment decisions and responsibility lie with the reader.

1. The HBM density peak is real

As I have said in several of my articles, the current trend is moving toward reducing HBM density and increasing bandwidth. Of course, this has not yet been officially announced, but reports from various parts of the industry are confirming this.

Of course, this decision is understood to be largely due to memory supply. This is because there are not enough HBM wafers to supply stacks with 12 layers in the quantities needed for the logic and CoWoS capacity NVIDIA has secured. The customer appears to have made this decision because moving to 8 layers instead increases yield and ultimately makes it possible to produce more HBM stacks.

Another reason is the increase in HBM prices in 2027. Even when GPU demand exceeds supply, NVIDIA has to give up some margin if component costs rise, and memory accounts for the largest share of those costs. NVIDIA has also notified major customers that it will raise server prices by more than 15% starting with shipments in early 2027.

However, the bigger issue is that this is not necessarily only because of supply and cost. There are also reports that customers reduced it because of power draw or thermal dissipation at the system level. Also, using NVLink to scale up after HBM density despec may have been, to some extent, the optimal configuration the customer wanted, both for processing AI workloads and at the system level. If this is true, it also means that the architecture and workloads are changing at the system level.

In fact, I have conveyed this to my paid subscribers several times on my Substack over the past month. NVIDIA has actually requested samples with 4 layers for HBM4 from memory vendors, and although they rejected this proposal, people in the industry currently think they may have to reconsider for HBM4E. There is also talk within the industry that the hardware team at a certain frontier lab is planning to use 4 layers starting with HBM4. It is reasonable to see this as a structural change that goes beyond a simple issue of supply and cost.

Subscribe now

2. Memory suppliers decide allocation based on revenue per wafer

When memory suppliers decide whether to use wafers for HBM or general purpose DRAM, the number they look at is the revenue from one wafer. Currently, HBM uses about 3 to 4 times as many wafers as general purpose DRAM for the same 1GB. This is the figure Micron disclosed when comparing HBM3E with DDR5. The December 2025 report that Samsung Electronics would convert some HBM3E lines to DDR5 and LPDDR to secure around 80,000 wafers per month, and the June 2026 report that SK hynix would delay the conversion of HBM3E lines to HBM4 and use them for DDR5, are also in the same context.

Then why sell HBM when they could just sell DRAM?

The reason is contracts.

The HBM being sold now is the annual contract volume signed in the second half of 2025, before the price reversal, and it has volume commitments and prepayments attached. So suppliers fill the contracted volume but do not add beyond it, and converted to DDR5 only where they could. According to stories from the industry, suppliers are asking for +70 to 140% in the 2027 negotiations.

Another thing to know here is that memory companies’ contract structures are changing to long term supply agreements (LTAs). Samsung Electronics said it would tie up 60 to 70% of its total DRAM and NAND capacity, not just HBM, in long term supply agreements of 3 to 5 years. SK hynix is pursuing a contract for general purpose DRAM with Google for 5 years, and Micron is selling about 20% of its volume under contracts covering multiple years with a price floor. This long term supply agreement structure could also directly affect DRAM prices in 2028.

Subscribe now

3. Three new fabs will increase wafer supply in 2028

The biggest reason many people say a memory downcycle could come in 2028 is the construction of new fabs.

Indeed, Yongin Y1 targets its first cleanroom opening in February 2027, Micron Idaho its first wafer in the second half of the same year, and Samsung P5 operation in 2028.

In the end, I think these three points will determine the memory downcycle in 2028.

First, how many HBM wafers are left over when the layer count is reduced? Does it will reducing the layer count really hurt memory vendors’ profits?

Second, what will happen to 2027 HBM contract prices? How will these HBM contract prices determine the downcycle in 2028?

Third, what will happen to general purpose DRAM supply and demand, and will the HBM premium offset this? What effect will this have in 2028?

From here, I will look at each point in detail and analyze each scenario to examine the memory downcycle in 2028 that many investors are worried about.

Subscribe now

Read more

This article was written in collaboration with and summarizes a conversation and I had about memory that lasted nearly two hours. You can also read it on the their Substack.

Subscribe now

Author: Daniel Koss in collaboration with Damnang.

Many of you will already know Damnang from his writing on X. I recently sat down with him for a conversation about one of the most important parts of the AI infrastructure stack: memory.

Damnang is a semiconductor engineer working in Silicon Valley. His background is in digital chip design, and he follows memory and the broader semiconductor industry closely.

We started with the basics. What is memory? Why do we need different types? And why does AI change the equation?

Then we moved to the questions that matter to investors. Can memory prices keep rising? Does more capacity inevitably mean another downcycle? How much power does NVIDIA have over its suppliers? And how should we think about the different memory companies?

What I found most valuable was where his engineering perspective challenged my investing perspective. He sees important technical advantages at Samsung, understands the appeal of SK hynix, and ultimately chooses Micron for his own circumstances.

To respect Damnang’s anonymity, this interview is being published in text only. No audio or video accompanies this article.

Below are my key takeaways, a company-by-company summary, and the edited interview.

Editorial note: This is an edited interview, not a verbatim transcript. The preliminary getting-to-know-you conversation, filler, repeated phrases, and off-topic digressions have been removed. Questions and answers have been tightened for readability, and clear transcription errors have been corrected. Several unclear figures and unverified anecdotes have been omitted. Forecasts, estimates, and industry commentary remain the speakers’ opinions at the time of the conversation. The takeaways and closing section are my interpretation, separate from Damnang’s answers.

Key Insights

1. The question is not simply “HBM or NAND?”

Damnang’s starting point is the memory hierarchy. Different technologies serve different purposes, with trade-offs between speed, capacity, and cost. His view is that AI is forcing the industry to rethink how those layers fit together, rather than creating one memory technology that replaces everything else.

My takeaway: The better investment question is which architectures become widely adopted, and which companies supply the layers those architectures need. Being bullish on memory does not require believing that every memory product will benefit equally.

2. Smaller models do not automatically mean less aggregate memory demand

He pushes back on the idea that model efficiency necessarily undermines the memory thesis. A smaller model can require less memory for an individual task, while more applications and more model calls increase aggregate demand.

My takeaway: We need to separate memory per workload from the total number of workloads. Efficiency is only one side of that equation. Whether usage grows enough to offset it is the question, not something that can be settled by looking at model size alone.

3. His longer-term thesis is about quantity, not endlessly rising prices

One of his clearest formulations was the distinction between P, price, and Q, quantity. He does not expect memory prices to rise without limit. Customers have their own economics to protect, and NVIDIA has considerable negotiating power in his view.

My takeaway: A durable bull case should not depend entirely on another round of price increases. The more interesting question is whether suppliers can grow volumes while maintaining attractive pricing and customer relationships.

4. HBM and custom memory may give suppliers more control over product mix

Damnang argues that today’s suppliers have more ways to allocate production than in earlier commodity-memory cycles. Producing more HBM absorbs capacity that could otherwise support conventional DRAM, while custom products offer another route away from undifferentiated supply.

My takeaway: His argument is not just that AI demand will rescue the industry. It is also that the supply side is changing. That is a reason to examine the old cycle framework more carefully, not a reason to declare that oversupply has become impossible.

5. Manufacturing memory and controlling its design are different sources of value

Our discussion of custom HBM kept returning to the logic at the base of the memory stack. Who designs it? Who owns the relevant intellectual property? And how much of that value stays with the memory supplier rather than NVIDIA or another technology provider?

My takeaway: More sophisticated memory does not automatically mean all the incremental profit goes to the memory manufacturer. We also need to understand who controls the architecture and the design.

6. The strongest technology is not automatically the best stock for every investor

He sees advantages in Samsung’s combination of memory, foundry, and logic capabilities. But we also discussed organizational complexity, internal incentives, and the difference between technical integration and pure exposure to the memory thesis. His personal choice was Micron, partly because of his U.S. circumstances and concerns about accessing Korean stocks.

My takeaway: Technology, business structure, and the security you actually buy are three separate questions. His Micron preference should not be misrepresented as a claim that Micron leads every technology category.

7. The NAND thesis is broader than one new memory architecture

Damnang’s view is that persistent storage remains necessary even as the faster layers evolve. He sees HBF as potential additional upside for Sandisk, rather than the entire reason to care about NAND. Importantly, he also acknowledges other NAND suppliers. This is not a claim that Sandisk has no competitors.

My takeaway: Separate demand for a storage category from one company’s ability to capture it. Capacity, execution, contracting, competition, and the price paid for the stock still matter.

8. His assessment of China is about equipment and execution, not just lithography

He believes concerns about Chinese memory supply often focus too narrowly on EUV and DUV. His argument also includes inspection, testing, and the wider equipment chain. He remains skeptical about how quickly that entire capability can be replicated, while explicitly acknowledging that CXMT is real and progressing.

My takeaway: Neither “China cannot do it” nor “China will immediately flood the market” is a sufficient analysis. His timing assessment is a forecast to test, not a certainty to build into a model without further work.

The Companies, at a Glance

This summarizes Damnang’s views in the interview. It is not a valuation model, a ranking of expected returns, or a set of current trading recommendations.

The Full Interview

1. What Is Memory, and Why Does AI Need So Much of It?

Daniel: Let’s start very simply. What is memory? When people talk about memory companies, what do those companies actually do?

Damnang: Memory stores data. When a computer is doing something, it needs to store information so that it can use it for the next operation.

You can compare it to a human brain. When we do something, we remember information and use it again. Computers, processors, and AI accelerators also need somewhere to store the information they work with.

The reason we need much more memory now is that we are asking computers to perform increasingly complex tasks through AI. Our brains have a very efficient architecture. We can store information, and sometimes we ignore it or forget it. A computer works differently.

As we try to make computing behave more like human intelligence, the amount of information that has to be stored and handled becomes much larger. That is why memory is so important for AI.

Daniel: At a high level, how would you explain the different types of memory to someone who is completely new to the industry?

Damnang: The first concept to understand is the memory hierarchy.

Imagine you are studying in your room. You keep a book on your desk because you can reach it immediately when you need some information. But you cannot keep every book on your desk.

For more information, you might go to a library. The library has much more capacity, but going there and finding the book takes time.

Computers have the same problem. If you want very fast access, you keep a relatively small amount of memory close to the processor. If you want to store much more information, you use another layer, but accessing it takes longer.

That is the memory hierarchy. You can imagine it as a pyramid. Near the top is very fast memory such as SRAM, but the capacity is small because it is expensive. Other layers provide more capacity at different costs and speeds.

Daniel: SRAM stands for static random-access memory, and DRAM is dynamic random-access memory?

Damnang: Yes.

SRAM is implemented using the kind of logic technology used for processors. When you design and manufacture a CPU or GPU, SRAM can be implemented using that fabrication process. That is expensive.

DRAM has a different structure and its own fabrication process. A DRAM cell uses a transistor and a capacitor. That allows you to make much more memory at a lower cost than SRAM.

Then you have NAND flash, SSDs, and hard drives further through the storage hierarchy. The important point is that they do different jobs.

For AI, the traditional arrangement is no longer sufficient by itself. With a smartphone application or a game, you have a relatively familiar kind of workload. AI has a very large amount of data to handle, and different types of data need different treatment.

For example, some data, such as KV-cache data, needs very fast reads and writes. We can call that hot data.

Other information is warm or cold. Cold data may still be necessary, but you do not need it immediately. You still need to store it somewhere, and that amount of data is also growing quickly.

That is why I think the AI era is redefining the memory hierarchy. People are discussing HBF, using more HBM, or putting much larger amounts of SRAM into wafer-scale chips. There are many possible ways to address the problem, and the final architecture is not settled.

2. Why More Efficient Models Can Still Mean More Memory Demand

Daniel: Presumably, the right architecture also depends on the use case.

As an extreme example, you could want an enormous context window and accept that it is very slow. Or you could want a much smaller context window with an almost instantaneous response. Those would imply different priorities for memory.

That makes the investment question harder, because both the use cases and the architectures are evolving. Is the broad point that AI is very data-hungry, even if it is difficult to predict the exact mix of memory it will use?

Damnang: Yes, that is a good way to explain it.

Some AI models are getting smaller. People look at more efficient open-weight models and ask whether we will still need so much memory.

I do not think that conclusion is right. This is related to Jevons paradox. Even if an individual model becomes smaller, the total amount of data that we need to handle can keep increasing.

When I talk to AI engineers, they point to the work being done in China to make models more efficient under resource constraints. They are trying to reduce model size.

But look at how those models are used. Each call can be relatively small, while the total number of calls involved in an inference workflow grows very quickly. So you cannot look only at the size of one call. You also have to look at the total number of calls.

We are also still at an early stage of AI adoption. Chatbots are only one use case. As AI expands into other applications, we will need to handle much more information.

Computing can become more efficient, but I still expect the total memory requirement to increase.

Daniel: Let me make that more concrete. AI-generated video has improved a lot. It is getting to the point where many people struggle to distinguish some clips from real footage.

Suppose AI-generated video becomes vastly more common. Video is much more data-intensive than text. You move from kilobytes to megabytes to gigabytes very quickly.

Which type of memory benefits most from that? NAND? HBM? Or all of them?

Damnang: My answer is all of them. It is very difficult to say that one type of memory is the only winner, because SRAM, DRAM, HBM, and NAND each have different roles.

Take enterprise SSDs in an AI data center. You cannot simply replace that storage layer with DRAM, because DRAM is much more expensive. Each layer exists for a reason.

My thesis is that demand across memory should grow. But I would change your question slightly. Rather than asking which memory type is the only winner, I would ask which memory hierarchy becomes established.

3. HBF, Cerebras, and the Competition Between Memory Architectures

Daniel: What do you mean by a hierarchy becoming established?

Damnang: There are different proposed solutions to the same problem.

For example, Sandisk is working on HBF, high-bandwidth flash. The idea is to stack NAND and increase its bandwidth, creating another layer between HBM and SSDs.

Sandisk wants that approach to succeed because it creates another application for NAND flash.

NVIDIA can approach the problem differently, using DRAM, LPDDR, or other arrangements within its own ecosystem. Different companies have different technologies and different incentives.

The important question for investors is which of those approaches becomes widely adopted.

Some people dismiss HBF. Others think it could be an important innovation in the memory hierarchy because it offers a different combination of cost, capacity, and speed. We do not yet know which approach wins.

Cerebras is another example. SRAM is very fast, but ordinarily you have a limited amount of it because it is expensive.

Usually, a wafer is divided into many separate chips. Cerebras takes a different approach by using a wafer-scale chip, allowing it to use a much larger amount of SRAM.

It is another attempt to build a different memory hierarchy. Certain applications place a very high value on speed, so the best architecture can depend on the domain.

I do not know which one will win. That is why I want to follow which architectures become dominant rather than assume there is one universal solution.

Daniel: My approach as an investor is simpler. NVIDIA has such a strong grip on the industry and the supply chain that I would pay very close attention to whatever architecture it pushes.

Partly, that is because I trust NVIDIA to understand the technical trade-offs and to change direction if it learns something new. But it also has the scale to drive adoption.

SK hynix depends heavily on NVIDIA. There is a relationship in both directions, but NVIDIA has other potential suppliers, including Samsung and Micron. SK hynix cannot simply replace all of NVIDIA’s demand with AMD overnight.

So for the near future, my instinct would be to follow what NVIDIA is building. Do you agree?

Damnang: I agree. That is why so many people focus on what NVIDIA does.

There are other HBM customers and users across the AI industry, including companies working on their own accelerators. But NVIDIA is a very important customer for the memory suppliers.

Daniel: Do you know roughly how much HBM demand comes from NVIDIA?

Damnang: I do not know the exact number. I believe it is more than half, but I cannot give you a precise figure.

The point is that NVIDIA accounts for a very large share of HBM demand.

That is also how I interpret NVHBM. NVIDIA has the power to influence the memory vendors, and NVHBM is another way for it to define the architecture and the rules that suppliers need to follow.

If you want to supply that ecosystem, you need to work within those requirements. Because NVIDIA is such an important customer, memory vendors have a strong incentive to do that.

4. The Memory Thesis: More Quantity, Not Unlimited Price Increases

Daniel: A lot of investors describe memory as the bottleneck. Could memory prices simply keep rising for the next several years?

I am asking about the price of memory itself, rather than just the stocks. Is there a fundamental reason that would prevent prices from continuing to go up?

Damnang: My belief is that the rate of price increases will eventually stabilize. NVIDIA and other customers will not be happy to accept unlimited increases.

That is why I keep saying this is a Q era, not a P era. P is price. Q is quantity.

If prices stabilize but quantities increase, suppliers can still grow revenue. That is also why memory vendors are interested in long-term agreements. They want more stable business and they want to keep their customers.

A higher price is not always better.

Daniel: Because at some point you are taking too much of your customers’ margin. They earn a lower return, and then the next round of investment becomes harder for both sides.

Damnang: Exactly. It also matters for hyperscalers’ capital spending.

Daniel: There is a parallel with NVIDIA. Part of the incentive for hyperscalers to develop their own custom chips is how much they pay for NVIDIA’s products.

Even if they like the products and the company, there is an economic incentive to find alternatives. The same principle should apply to memory suppliers. At some point, very high margins encourage customers to look for another solution.

So the healthier long-term outcome could be growing quantities, rather than pushing prices as high as possible.

Damnang: Right.

Further reading: For a concrete example of the trade-offs between memory specifications, production volumes, and supplier revenue, read Damnang’s What Does Rubin Ultra’s 8-Hi HBM Mean?, which examines the implications of a potential change in NVIDIA’s HBM configuration.

5. Does More Supply Inevitably Mean Another Downcycle?

Daniel: But that creates another question. If the industry focuses on increasing quantity, could it build too much capacity and create the next downcycle?

From my perspective on AI infrastructure, I expect demand to grow much faster than supply. Even substantial improvements in efficiency might not keep up with how much AI usage expands.

How do you think about that balance in memory? How quickly can supply really grow, and how worried should we be about oversupply?

Damnang: This is one of the questions I hear most often from investors and other industry people.

Companies are building more fabrication capacity, and China is also trying to expand. Investors worry that more supply will arrive around 2028 and bring another memory downcycle.

I disagree with the idea that this automatically leads to the same outcome as previous cycles. There is an important difference in the product mix.

I am not going to base the entire argument on AI demand. We can expect AI demand to grow, but nobody knows exactly how much it will grow.

The other part of the argument is that memory vendors now have more ways to manage their supply.

They did not previously have today’s HBM business alongside their conventional DRAM business. Now they can allocate more production toward HBM. Producing HBM absorbs a large amount of DRAM production capacity, so the mix matters for how much conventional memory reaches the market.

That is also one reason they want a more differentiated portfolio and more custom memory. Custom memory is an important part of my thesis. It gives suppliers another way to move beyond the traditional commodity model.

I am working on a supply model, although it is not finished and I still need to check it.

At this stage, I see supply coming in below what the market consensus expects.

There are several reasons. One is that Chinese supply may grow more slowly than people assume. Another is that HBM affects how vendors allocate their memory capacity. Pricing and the HBM premium also influence those choices.

Then there is the move toward custom memory and memory-on-logic. The product mix is becoming more differentiated.

Taken together, I think those factors reduce the supply risk relative to what many investors expect.

6. SK hynix: A Strong Memory Business, but Who Controls the Value?

Daniel: Let’s go through the individual companies, starting with SK hynix.

To me, SK hynix looks like a strong risk/reward candidate because it is closely tied to NVIDIA and has exposure across NAND, DRAM, and HBM. Some investors view that NVIDIA relationship mainly as a risk. I also see it as being close to the center of the industry.

There is debate about how the competitive position changes with HBM4, particularly versus Samsung. There is also the valuation comparison with Micron and the question of a Korean discount.

What stands out to you about SK hynix?

Damnang: The NVIDIA relationship is important, but it is also a risk.

I have heard industry rumors about NVIDIA trying to negotiate lower HBM prices with SK hynix. NVIDIA is a powerful customer and can work with Samsung, SK hynix, and Micron.

My understanding is that Samsung’s HBM4 has advantages in some specifications, such as bandwidth or pin speed, compared with SK hynix’s offering. That gives NVIDIA something it can use in negotiations.

It can say: look at the alternative, look at its performance, and explain why I should pay your price. I am describing the negotiating dynamic. The specific pricing conversations I have heard about are rumors.

The second issue is that SK hynix is a memory-focused company, like Micron. Samsung also has logic and foundry capabilities.

As memory becomes more customized, those capabilities become more important. Samsung wants to show that it can do more than manufacture memory. It can also contribute on the logic side.

I understand that SK hynix is also building its own logic and memory-on-logic capabilities in the United States. That understanding comes from industry conversations.

It also wants to diversify demand. I have heard about efforts to expand business with AMD and other customers.

Daniel: A stronger AMD would presumably be helpful to the memory suppliers because it would reduce their dependence on one dominant customer.

Damnang: Yes.

During the HBM3 period, SK hynix was in a very strong position relative to Samsung and Micron. Other customers wanted access to its supply.

The competitive situation is changing. So SK hynix has reasons to broaden both its customer base and its own capabilities.

The two risks I would emphasize are NVIDIA concentration and the need to strengthen its logic-design capabilities.

Daniel: Can you explain what you mean by logic-design capabilities? Why do those matter for a memory company?

Damnang: Think about custom HBM and the base die underneath the memory stack.

You can put more logic there, such as memory-controller and interface functions. That is different from making the memory cells themselves. It requires a different process and different design capabilities.

Samsung has its own foundry, so it can use that capability for the base die. SK hynix works with TSMC.

Daniel: But is that necessarily a disadvantage? Doing everything in-house means more vertical integration, but also more complexity.

Working with TSMC could be an advantage if it gives you access to a very strong foundry. Why is owning the foundry or the logic capability better?

Damnang: Those are two different issues.

First, TSMC has capacity constraints too. But more importantly, TSMC can manufacture the base die. Who designs the logic on it?

If the memory supplier can design and implement that logic and owns the relevant intellectual property, it can capture more value.

Think about a company such as Broadcom. A lot of its value comes from the design capabilities and intellectual property it contributes to custom chips.

Samsung has memory-related and logic-related intellectual property. SK hynix needs to strengthen its position there. Otherwise, it may need to rely more on NVIDIA’s intellectual property or third-party providers such as Synopsys and Cadence.

That affects how much value it captures from the logic side.

This is why I keep returning to the shift from commodity memory toward custom memory. It is not only about producing a more advanced memory stack. It is also about who contributes and owns the design.

Further reading: Damnang explores this question of design ownership and bargaining power in more detail in What NVHBM Means: The Contest for Power Over HBM Begins.

7. Micron: You Do Not Have to Be the Technology Leader to Benefit

Daniel: As an investor, Micron can look a bit like a U.S.-listed version of the memory thesis at a higher valuation than SK hynix.

I have also heard secondhand comments that its engineering culture and yields are very strong, but I do not know how reliable those comments are. How do you see Micron’s technology and its position in the market?

Damnang: My view is that Samsung and SK hynix are the strongest two technologically, and Micron is third. I do not expect that technology gap to disappear quickly.

But that does not mean Micron cannot do very well.

I would compare it with AMD. I do not expect AMD to overtake NVIDIA, but AMD can still grow significantly because the overall AI market is growing so quickly.

If the market expands enough, there are customers and opportunities that one supplier cannot serve on its own. Another supplier can grow substantially without becoming number one.

I think about Micron in a similar way.

Micron also has a geographic advantage from its U.S. position, in my view. So when I invest in Micron, I am not simply making a statement that it has the best technology.

I am expressing a bullish view on memory and a view on U.S. policy. Those are important parts of the investment case for me.

8. Samsung: Technical Integration Versus Organizational Complexity

Daniel: From your comments, it sounds as though you see important technical advantages at Samsung. It has memory, foundry, and logic capabilities, which could mean more intellectual property and more potential value to capture.

But as an investor, Samsung’s diversification is also what I like least about it.

When I buy a memory stock, I want exposure to the memory thesis. Samsung also has phones, TVs, and a lot of other businesses. It is a very large organization, and I worry about the complexity and internal politics.

SK hynix feels like a more focused way to express the thesis. At the same time, I understand your argument about vertical integration.

How do you weigh those two sides?

Damnang: I agree with the concern. Samsung’s size and structure create risks.

One issue I hear about is compensation across different divisions. When memory performs very well, people in other businesses can feel that their compensation does not reflect their contribution.

Even within semiconductors, people working on logic or in the foundry can ask: we help make the custom HBM base die, so why do we not receive the same rewards as the memory business?

I hear those complaints from people in the industry. Some engineers are very unhappy with the internal policies and culture.

That is a risk because these teams need to work together.

Daniel: As a founder, I also see another side to that. When talented people become frustrated with internal politics, some of them leave and build something new. It can create opportunities for other companies and for innovation outside the organization.

Damnang: Yes. But for Samsung itself, it is a real concern.

I have heard examples where someone needed help from another team, but the person on that team did not want to take on more work because they felt their compensation was not fair.

If you need collaboration between memory, logic, and foundry teams, that kind of incentive problem matters.

So the technical ability to combine those businesses is one thing. Getting the people and the organization to work together is another.

9. Sandisk: A Commodity Can Still Have a Supply Constraint

Daniel: Sandisk has surprised me. When I first started looking at memory, much of the discussion focused on the big three and HBM.

The argument was that HBM is difficult to make, only a few companies can produce it, and other types of memory are more like commodities. But Sandisk’s stock has had an enormous rally.

How do you think about the company and the idea that NAND is a commodity?

Damnang: There are a few parts to it.

First, memory vendors want to move toward more differentiated products. For Sandisk, HBF is one possible route. If HBF succeeds, that could provide additional upside.

Second, I understand the concern that the stock has already gone up a lot. There has been a lot of excitement, and I partly agree with people who say a substantial amount of upside may already be reflected in the price.

Another part of the story is long-term agreements. Because the existing product is more commodity-like, Sandisk can try to make the business more predictable through customer commitments.

One route is changing the product through something like HBF. Another is changing how the existing production is contracted.

My understanding from industry conversations is that Sandisk wants a much larger share of its business covered by long-term agreements, and that it does not want to add substantial new fabrication capacity without those commitments.

That is a way of managing the supply expansion rather than simply building more and hoping the demand is there.

Daniel: But how do we reconcile two ideas: that NAND is a commodity, and that customers do not have an immediate replacement?

To me, a commodity sounds like something that is easy to substitute. Where does the bargaining power come from?

Damnang: There are other NAND suppliers. Samsung and Kioxia, for example, can compete in this market.

The point is not that Sandisk is the only company that can do it. The point is that adding semiconductor supply takes time.

Even when we call something a commodity, it is not the same as saying that a competitor can immediately produce as much as the market needs. It still takes time and capability to build that supply.

Daniel: So the important distinction is the delay between demand arriving and competitors being able to add capacity.

Damnang: Yes.

There is another point about the memory hierarchy. Much of the architectural change is happening in the middle layers. You can debate HBF or different arrangements of faster memory, but there is still a need for fast, reliable SSD storage.

If you make the rest of the system more efficient, a lot of cold data or information that is not immediately being used still needs somewhere to go. That supports the need for NAND flash.

So I am interested not only in which new architecture wins, but also in the storage layer that remains necessary underneath it.

That is why I see the NAND layer benefiting across different possible architectures.

Further reading: For a deeper look at HBF’s technical trade-offs, adoption prospects, and potential financial impact on Sandisk, read Damnang’s Will HBF Create Upside for Sandisk?.

10. CXMT and China: Look Beyond EUV Versus DUV

Daniel: Let’s talk about CXMT, both as a company and as a potential source of competition for the other memory suppliers.

How do you think about it?

Damnang: I understand the concern. People hear that China is expanding memory production, and they worry that supply will increase enough to cause another downcycle.

But CXMT requires a different investment framework because of the Chinese government’s role. I expect it to receive support even if it does not make money.

That is different from evaluating a company only on its commercial economics.

On the technology side, my view is that there are still gaps between CXMT and the leading memory suppliers. I also think some of the discussion about the Chinese competitive threat is exaggerated.

Daniel: Personally, I do not invest in Chinese stocks. That is not about taking a political side. It is about the risks I am willing to accept as an investor.

I worry about government intervention and about whether the interests of outside shareholders are protected. I also worry that heavily subsidized supply can change the economics for the rest of the industry.

So I have concerns both about owning the stock and about the impact additional supply could have on competitors.

Damnang: I recently spoke with Chinese investors who also had concerns about investing in CXMT. They were looking at the technology and other investment risks, and some preferred other memory companies.

The point I especially want to make about the supply risk is that people focus too much on EUV and DUV.

They say: China does not have EUV, but it can build more DUV equipment, so memory capacity will increase.

But making memory chips requires far more than lithography equipment.

You need inspection, testing, and many other types of semiconductor equipment. Companies such as KLA and Applied Materials are part of that broader equipment ecosystem.

The equipment restrictions and limitations are not only about EUV. You have to look across the entire manufacturing process.

Some reports say China can make all of these tools itself. My view is that replacing that whole equipment chain takes a long time. It is not something that happens immediately.

In my view, Chinese supply will not affect the market before 2030.

Editor’s note: This is Damnang’s forecast, not a verified supply estimate. State support for a business also does not guarantee a positive return or protection against loss for its shareholders.

Daniel: That is the issue with jumping from “China is entering the market” straight to “everything becomes worthless.” You still have to understand the technical and manufacturing constraints.

Damnang: Exactly.

11. Is the Rally Over? And Which One Stock Would He Choose?

Daniel: To finish, let’s talk about the stocks at the prices prevailing when we are having this conversation.

Are you still bullish on memory, or do you think the rally has run its course?

Damnang: I do not think it is over. I still strongly believe there is another leg to the memory rally.

If you believe the longer-term memory thesis, small differences in the entry price matter less than whether you believe the stocks can go much higher. I think there can still be substantial upside, potentially a doubling.

Daniel: So you are broadly bullish on SK hynix, Micron, Samsung, and Sandisk. What about CXMT?

Damnang: CXMT could also do well, but it is not something I am focused on for my own portfolio.

I also want to be clear that CXMT is not a scam. It is doing real work and progressing quickly. I just do not think its competitive impact is as large, as quickly, as some people currently argue.

For memory stocks more broadly, the market may need some time to digest the rally. Investors take profits, and then they may reinvest as the next view of the sector develops. But I remain bullish.

Daniel: Let’s make it a forced choice. If you could own only one memory stock, which would you choose?

Damnang: For my own circumstances, Micron.

Daniel: Why Micron?

Damnang: I am in the United States, and I do not want to deal with the Korean stocks right now.

As I said, Samsung and SK hynix have very strong technology and can be good investments. But there are other risks to consider, including the way you access the Korean stocks.

For example, I am concerned about premiums on depositary receipts. If those issues changed, I could reconsider. But given the situation as I see it, I would choose Micron.

I already have a substantial portion of my portfolio invested in it.

Daniel: Interesting. Thanks for the conversation.

My Closing Takeaway

The most useful part of this conversation was not a single ticker. It was the distinction between several questions that often get treated as though they are the same.

What does AI need more of? Which technologies are best suited to those needs? Which companies control the relevant designs and capacity? And which stock is the best way to express that view for a particular investor?

Damnang can be bullish on the memory sector, see technical strengths at Samsung and SK hynix, and still prefer Micron for his own portfolio.

Likewise, we can believe that NAND demand grows without assuming Sandisk is a monopoly. We can take Chinese competition seriously without assuming that an entire semiconductor manufacturing ecosystem can be replicated overnight. And we can believe that HBM changes supply dynamics without concluding that memory will never experience another downcycle.

For me, the most important question to keep following is how the memory hierarchy evolves, and who captures the value as it does.

Disclaimer

This article reflects my personal opinions and is provided for informational and educational purposes only. It does not constitute financial, investment, legal, or tax advice, nor a recommendation to buy, sell, or hold any security. I may hold positions in companies mentioned and may change these positions at any time without notice. Past performance is not indicative of future results, and investing involves risk, including the possible loss of principal. Always do your own research and make your own independent investment decisions.

Memory now accounts for a larger share of AI system cost, so taking the lead in deciding how the memory that computation needs is connected, and who can supply it, can become a new form of power.

This article starts with why the memory hierarchy is growing more layers in the AI era. It then goes through the technologies and companies competing at each tier, the changes expected through 2030, and the events to check over the next 12 months, and offers an outlook on each.

Disclaimer

This article is for information only and does not recommend buying or selling any particular stock. Data is as of September 8, 2026. Company announcements, supply-chain estimates, and the author’s own assumptions are kept separate, and estimates may differ from market consensus. The author may hold positions in the companies mentioned and may change them without notice. Investment decisions and their consequences are the reader’s responsibility.

Subscribe now

1. The simplified memory hierarchy before the AI era

As a rule, faster memory is more expensive and holds less.

So a computer uses several kinds together: SRAM inside the processor, DRAM as working space, and NAND SSDs for long-term storage. Data that is used often goes on the fast side, and data that is not needed right now goes on the cheap side.

The familiar library analogy makes this easy to picture. When you study, you keep the material you need right now on your desk where you can reach it, but the desk cannot hold much, while the vast amount of other material sits in the library, which takes time to reach. The way a computer uses memory is not much different.

Until now, the memory hierarchy has been as simple as the figure below, and the amount of computation to be done was handled reasonably well within that simple structure. DRAM interfaces such as DDR were defined jointly through JEDEC, the semiconductor standards body, and memory makers supplied products to those standards. There were differences in process and yield, but what moved commodity DRAM prices was the supply and demand cycle. When demand rose it was a supercycle, and when supply rose it suddenly turned into a downcycle. Memory has been a commodity in the fullest sense.

Subscribe now

2. The problem HBM solved, and the problem that remains

With the AI era, this simple hierarchy started to change.

In the library analogy, it used to be enough to keep the few books you needed on the desk (DRAM) and leave the rest in the library (SSD). Large AI models are different. Producing each character of an answer is like rereading every book in the library from cover to cover, so the entire collection has to be on the desk, and it has to be flipped through quickly every time. Conventional DRAM had room to hold the books, but not the speed to flip through them.

So a new tier was inserted into the hierarchy. HBM is memory made by stacking DRAM chips vertically, tying them together with a wide path, and placing them right next to the GPU. It is as if the desk were pulled up beside the GPU and rebuilt so that several books could be flipped through at once. How much data can be moved at a time is called bandwidth, and HBM’s bandwidth is far larger than that of ordinary DRAM modules. That is what let GPUs cope with rereading the whole model every token, and the HBM attached to each GPU has grown with every GPU generation.

The problem is capacity and price. The number of HBM stacks that can be placed around a GPU is limited by package area. To keep the same design, the stack height or the capacity of each DRAM die has to grow, but taller stacks worsen heat and yield, and adding more stacks means redesigning the GPU and the package. HBM also consumes far more wafers than commodity DRAM for the same capacity.

On top of that, HBM prices rose sharply in 2026, making the approach of putting all the needed data in HBM a heavier burden. There is a limit to how far the desk can be widened, its price is going up, and the pile of books that has to sit on it keeps growing. So the next question became whether every book really needs to be on the desk.

Subscribe now

3. Data used often and data that waits

The data an AI model handles falls into two broad kinds.

One is the weights, the numbers that hold what the model learned; in the analogy, the books.

The other is the context, the content of the question and conversation being processed right now. In the analogy, the notes spread out on the desk.

Both split into a part that is used often and a part that is not.

Let’s see the weights first.

In a dense model that uses every weight every time, each token (the unit in which the model processes text) requires reading every book, so the whole collection must be on the desk. But most large models today use an MoE structure. The model holds several groups of experts, and for each token it picks only the ones it needs. DeepSeek V4 Pro, released in April 2026, has 1.6 trillion parameters in total but uses 49 billion per token (DeepSeek release). The model still has to own the whole collection, but producing one token opens only about 3% of it.

That splits the weights into two groups.

Experts selected often are hot weights, and experts selected rarely are cold weights. The frequently used ones stay on the desk, that is, in HBM, and the rarely used ones can move to cheaper memory.

That does not mean every expert unused in one token can be pushed down to slow memory. The next token, or another request, may need that expert. When many requests are processed at once, the range of experts needed widens. How much can actually be moved depends on selection frequency and on how fast the data can be brought back.

Next is context.

Context is stored in the form of a KV cache. It holds the intermediate results produced while processing tokens, so the model does not recompute the context it has already read from scratch each time; in the analogy, the notes on the desk. One is created for each request that has its own context, such as a single conversation or a single agent task. Broadly, the longer the context and the more requests there are, the more storage is needed.

The KV cache can also be divided by usage state. The cache of a request that is generating an answer right now is read often and has to be quickly accessible. In typical GPU inference, HBM plays that role.

By contrast, a request that is waiting for a tool to run or for a person to reply does not read its cache until the next turn. Keeping it in HBM leaves less room for other requests; discarding it means recomputing the context later. So the cache is kept outside HBM and brought back when needed. This is called KV cache offloading. NVIDIA also described moving rarely used context to host memory and storage in its August 24 material (NVIDIA).

Subscribe now

4. How to use capacity outside HBM

Model designs that compress the KV cache are also advancing, so storage per token is trending down. But if context length and the number of concurrent requests grow faster than that, total storage still increases. The more requests are waiting, the stronger the case for keeping their context somewhere cheaper than HBM.

The “attached memory” discussed here means memory outside the GPU package: the HBM of other GPUs, host DRAM attached to the CPU, DRAM expanded over the CXL interface standard, and SSDs that exchange data directly with the GPU. The communication paths that link them are the interconnect.

Being connected does not make all of it as fast as a GPU’s own HBM. Reaching memory on another GPU or another rack means going through links and switches. Optical links extend the reach, but actual bandwidth and latency depend on link speed and topology. So which data sits on which GPU and in which memory becomes important.

The figure above shows the direction in which this kind of placement is spreading. As I said in the introduction, the once simple memory hierarchy is heading toward something more layered. The middle tiers in the figure are still contested, in both technology and in how they will be adopted.

Recent industry announcements also suggest that a trend toward less HBM capacity per GPU package is close to settled. This is the so-called HBM density despec. I have covered it in several articles, and readers who are not yet familiar with it may want to read those first.

To sum up, the industry is shifting the money that would have gone into HBM capacity toward the interconnect, and, looked at more broadly, it is fighting a quiet war to build out a memory hierarchy that has not yet been formalized.

Subscribe now

5. The same rack can hold more context

As we saw in Section 3, let me do a simple calculation of why moving the context of waiting requests to cheaper memory outside HBM lowers cost. The numbers below are example assumptions meant to show the method; they are not measurements of any product or service. Changing the assumptions changes the absolute figures, but the ratios move the same way.

Take one NVL72 rack with 20.7 TB of HBM, and use 0.8 TB for model weights, leaving 19.9 TB. The 0.8 TB is a simple calculation of 1.6 trillion parameters all stored at 4 bits. In a real deployment, of course, more is needed for metadata, working space, replicas, and so on.

If the KV cache of one 200K-token request is 2 GB, the remaining space can hold about 10,000 contexts. That assumes 10 KB per token and is not a measurement of any particular model.

Now assume that only 20% of requests are generating an answer and the other 80% are waiting. This ratio is an assumption about how much of an agent’s time is spent waiting, and it is the least certain assumption in this calculation. Move the caches of the waiting requests to host DRAM or SSD, and only the caches of active requests remain in HBM. The same HBM can then keep about 50,000 contexts.

This 5x is a ratio of how many contexts can be kept, not of processing speed. It is also an upper bound based on capacity alone, leaving out compute and transfer latency. If the time to bring a cache back exceeds what the service can tolerate, the full 5x cannot be used. If the cache were 100 KB per token, both request counts would fall to one tenth, but under the same assumptions the ratio stays at 5x.

Offloading can reduce the burden of buying more racks for lack of capacity, or of repeatedly recomputing discarded context. Services whose agents spend long stretches waiting in the middle of a task have the most to gain.

In exchange, more host DRAM, SSDs, controllers, and interconnect are needed. Part of the money saved moves to those parts. On NVIDIA’s platform, the configurations and certifications NVIDIA sets have a large say in which suppliers are chosen. On shared standards, customers have more room to combine modules and SSDs from several suppliers.

From here, the article looks at who captures this new demand: the standards competing at each tier, the technologies that become products first, the conditions under which memory makers' bargaining power changes, and finally the size of the demand and the events to check.

Read more

The last Optical Investing Round Two piece covered why this is a good moment to look at optics again, and roughly how the names sort out.

This one redraws the map as of September 2026, converting the direction of optical technology, the valuation of each stock, and the expectations already priced in into factors.

Optics is still out of the spotlight, so I go through it in detail:

the stocks that can produce good returns from here,

the ones worth picking up if they fall a bit further,

and the ones worth owning now even at a slightly higher price.

Disclaimer

This article is for information only and does not recommend buying or selling any security. Prices and multiples are as of the September 3, 2026 close and go stale with time. Earnings estimates are market consensus and may differ from actual results. The author may hold positions in the securities discussed, and those positions can change without notice. All investment decisions and their outcomes are the reader’s own responsibility.

NFA / DYOR.

Subscribe now

1. The Correction Came From the Multiple, Not the Numbers

Why optical stocks are falling now

As of September 3, the 13 names in the optical map are down 42% on average from their 52-week highs, while the S&P 500 sits 0.8% below its high and NVIDIA 3.4%, so this was not a market-wide sell-off.

Yet all 11 names that reported in the August earnings season grew revenue more than 20% year over year, and Corning was the only one whose next-quarter guidance came in below consensus.

When results hold or improve and only the price falls, the problem is not the companies but what the market will pay for them.

The first force cutting that price is rates.

In optics the profits from CPO, NPO, ELS, and OCS land in 2027 and 2028 rather than 2026, and the further out the profit, the more its present value shrinks when long rates rise. On the same move in rates, optical multiples get cut before the rest of AI hardware.

The second is the money being spent today to earn those distant profits.

AAOI, AXT, and Sivers funded expansion and operations with equity, and even Coherent, which did no offering, spent $1.1B on FY26 capex against $79.5M of operating cash flow, for roughly negative $1.02B of free cash flow. Once several companies were growing revenue at double digits while cash only went out, the market began applying capital-intensive-cycle multiples across optics.

If rates cut the multiple, cash burn pushes out the date it comes back.

Three pieces of news then made a multiple reset look like broken fundamentals.

NVIDIA’s CPO switch uses fewer lasers, Fabrinet lost datacom volume at its largest customer, and Credo’s GAAP gross margin came down. Those happened in three different layers, light sources, assembly, and connectivity ICs, but the market read them as one signal that optical dollars and margins were shrinking together. Taken apart, they show optical dollars moving between layers rather than disappearing.

What I Track: 30-year yield · AAOI remaining ATM capacity · FCF conversion at the major optical names · share reaction after guidance raises

Subscribe now

2. The Dollars Did Not Shrink. They Moved.

Why optics still deserves attention

Where those dollars go starts with money changing seats inside the AI system. As I laid out in HBM Density Peak in August, the lower HBM stack count in the Rubin Ultra generation does not mean HBM demand is rolling over; it means we have crossed into a stretch where how fast the data moves matters more than how much memory sits next to the GPU. Cutting capacity per GPU is absorbed by a scale-up domain that ties 576 of them together, and the money that gets freed goes to the NPO and switching that bind the racks.

The same budget now buys less HBM and more of what connects the racks, so what matters in optics is not how many transceivers get sold but how much of the money that used to go to memory ends up in interconnect and optics.

Which companies that money reaches shows up in the supply chain NVIDIA disclosed. In the June production disclosure for Spectrum-X Ethernet Photonics, TSMC handles silicon photonics fabrication, SPIL packaging, assembly, and test, TFC the laser modules, and Foxconn system assembly. A later NVIDIA production update named Lumentum as a core partner.

NVIDIA’s developer blog describes a broader silicon photonics ecosystem in which Lumentum, Sumitomo, and Coherent supply ELS lasers and subassemblies, Corning and Coherent supply fiber and connectors, and Foxconn and Fabrinet handle system assembly. Coherent is ramping ultra-high-power CW lasers for CPO under its NVIDIA partnership in Texas and expects revenue recognition to begin in the December quarter. Within one program, in other words, the kind of dollars a company collects depends on which layer it stands in.

The timing differs by layer too.

1.6T pluggables are already ramping, OCS and scale-out CPO start showing revenue in 2H26, and DCI shows up in Ciena’s backlog and Fabrinet’s telecom revenue, while NPO and scale-up CPO matter more from 2H27 on.

Put those together and optical dollars are not shrinking; they are moving from front-panel module assembly toward light sources, materials, OCS, DCI, and scale-up interconnect.

So the names have to be picked by which side of that move they stand on, not by how far they have fallen.

What I Track: OCS revenue recognition · Coherent’s first CPO revenue · first ELS shipment · Rubin/NVL576 shipping schedule

Subscribe now

Technology direction as of September 2026: seven shifts and their weight

Sorting names by which side they stand on means first setting out what changes. I use only what has been confirmed in public materials since the April map and the March CPO specials.

Each shift is described in the same order: what changes, why now, when, and who wins and loses. Each shift gets a weight from 1 to 3. The criteria are the dollars that move by 2028 and how far the shift has been confirmed by orders or production. I start with shift zero, the 1.6T pluggable ramp (S0, weight 3), which is the largest dollar pool today.

200G EML and SiPh pluggables produce most of the revenue in 2026 and 2027, yet in the first shift below they stand on the losing side. That is the starting point of this piece, and the stock judgments start from this direction.

1. The electrical-to-optical boundary moves from the switch front panel into the package (S1, weight 3).

Today the signal leaves the switch chip as electricity and turns into light in a pluggable module at the front panel. At 200G per lane, the distance copper can carry a clean signal becomes shorter than the board, and the power spent restoring the electrical signal becomes a large share of total switch power. So the conversion point moves next to the chip (NPO) or into the same package (CPO).

NVIDIA formalized full production of its scale-out CPO switch in June, with a partner update in August, and for the scale-up links between GPUs, Lumentum and Coherent talk about 2H27 shipments and 2028 deployment. Winners are light sources, InP, fiber attach, and test. Losers are front-panel module assembly and, after 2028, in-rack copper. The checkpoints are the first shipment of scale-up light sources and the date the 448G electrical standard is fixed.

2. The light source leaves the module (S2, weight 3).

CPO cuts the number of lasers per switch to a quarter, but the remaining laser has to feed light to many channels, so its output rises to hundreds of milliwatts and reliability requirements rise with it. The laser stops being a part inside a module and becomes a separate, replaceable product called an external light source (ELS). Count falls; price per unit and InP consumption rise. Winners are high-power CW lasers and InP substrates, and the ELS suppliers NVIDIA names in its documents are Lumentum, Sumitomo, and Coherent. Coherent has 6-inch InP today; Lumentum’s arrives in 2028. Losers are businesses that sell many low-power lasers. Checkpoints are the first ELS delivery (2H27) and AXT’s quarterly capacity.

3. Optical circuit switches remove one electrical switching tier (S3, weight 2).

A network converts light to electricity at every tier, switches it, and converts it back. OCS steers the light path directly with mirrors (Lumentum, MEMS) or liquid crystal (Coherent), removing that conversion. The market opened when Google moved from in-house development to external sourcing; Lumentum guides to its first $100M-plus quarter in fiscal Q1 and Coherent talks about a market above $4B. The winners are those two companies; the losers are the electrical switch at that tier and the transceivers on either side of it.

4. Not dropping the link matters as much as speed (S4, weight 2).

In a training job that ties together tens of thousands of GPUs, one dropped link stalls the whole job. The market splits two ways. LPO removes the DSP from the module to cut power by 30% to 50% and leans instead on the precision of analog ICs such as TIAs and drivers (Semtech, MACOM). DSP companies sell features that keep links from dropping (Credo’s ZeroFlap). CPO moves toward removing the DSP entirely, so merchant DSP content per port shrinks, and Marvell answers with scale-up optics and Photonic Fabric. Winners are analog ICs and reliability products; losers are merchant DSP content per port.

5. Scale-up spreads across racks and scale-across links data centers (S5, weight 3).

This is the layer where the budget shift from memory density to connectivity shows up as physical wiring. Copper cannot leave the rack, so fiber takes the rack-to-rack links and coherent optics take the links between data centers. Corning’s form-factor-agnostic claim is not a slogan but a fiber-count calculation, and Ciena’s $8.5B backlog and Hyper-Rail are the first orders in this flow. Losers are copper interconnects built around a single rack.

6. Yield and test become the real bottleneck (S6, weight 1).

Once optics are inside the package, one defective optical die scraps the whole GPU package. Burn-in at the wafer stage (known good die) enters the process before packaging, and there is no standard yet. Aehr followed repeat orders from its lead SiPh customer with a second major SiPh customer in 2026, and a follow-on production order from that customer as well. The dollar pool is still small, but the production proof already exists. Losers are assembly margins in the parts of the flow where standards are absent.

Running through all seven shifts is one move:

the point where signals turn into light travels toward the chip, and in that move light sources, fiber, and test survive while front-panel assembly and merchant DSP content per port come under pressure.

S6 gets a weight of 1 not because it is a lesser bottleneck but because the dollars moving inside optics are small. Section 3 multiplies these weights by each company’s exposure to build the direction exposure score.

That was the technical direction for optical as a whole.

Knowing the direction, though, is not the same as knowing the investment. Even when the optical direction is right, it means little if that business is a small share of a company’s total results, and even a real bottleneck leaves limited upside once valuation already reflects the expectation. The average drawdown in this correction reached 42%, and that is why only three names still read as cheap to me.

From here I run the core optical names one at a time through my own optical investment model: what has actually been confirmed on the technology side, and how much the market has already paid for it. Six factors score each name, and they sort into three buckets: Mispriced, Conditional, and Worth paying up.

Read through to the end and you should come away with a clear investment view on how to prepare for the second round in optical.

Subscribe now

Read more

• Capex by the four largest hyperscalers is on track to exceed $700B in 2026. The demand signal is strong, but each layer responds on a different clock, and capacity further down the stack moves more slowly and less reversibly.

• Power and grid now govern the turn-on timing of new AI capacity. At the same time HBM and advanced packaging still gate the shipment of accelerators that have already been ordered. Bottlenecks move, but the earlier constraint does not disappear.

• Shortage on its own is not an investment thesis. Scarcity becomes pricing power only after passing through qualified supplier set, switching time, substitution path and contract structure. Only then is it worth asking whether that price amplifies into earnings through volume, content and operating leverage. The location of the bottleneck does not decide economic capture. The supplier set and contract structure around it do.

• My two calls are explicit. Power and grid are likely to remain the dominant constraint on new capacity at least through 2027, and data movement is likely to take a larger share of AI system economics through 2028. But bandwidth growth and optical revenue growth are not the same thesis.

Disclaimer This note is for information only and is not a recommendation to buy or sell any security. Company results are taken from official filings and releases; industry figures are taken from public reporting and third-party estimates. Third-party estimates vary by source, so they are better read for direction and structure than for absolute levels.

NVIDIA’s fiscal 2027 second quarter, reported in August 2026, put Data Center revenue at $89.0B. In the same month Lumentum passed $1B in quarterly revenue for the first time, and GE Vernova’s gas equipment backlog and slot reservations reached 116GW. Compute, optics and power are entirely different markets, but the incremental demand behind all three starts in the same place.

The AI infrastructure buildout.

The problem is that the same demand does not create the same economics.

As AI capex moves down the stack, supply response time, supplier concentration, switching cost and contract structure all change. What matters for investors is not which bottleneck is most severe.

It is who can convert scarcity into pricing power, and whose pricing power amplifies into earnings. This note redraws the AI infrastructure investment map on that basis.

1. The Six Layers: Follow the Demand Signal Down the Stack

Response Time Matters More Than Component Labels

Splitting AI infrastructure into component categories such as compute, memory, networking and power is easy. For investment purposes that classification is not enough.

What matters more is how quickly each layer can turn incremental demand into capacity, shipments or monetization.

The upper layers are software and capital allocation problems. Further down, physical capacity is required: wafers, packaging slots, electrical equipment, generation and grid connections. The further the demand signal travels, the larger the capital commitment, the longer the lead time, and the harder it is to reverse a wrong decision.

Layer 1: Demand.

Applications and agents consume tokens and create final demand. As of August 2026, press reports put OpenAI’s annualized revenue run rate near $40B and Anthropic above $65B. The two companies do not define revenue identically. What governs this layer is not a supply ceiling but monetization and willingness to pay.

Layer 2: Capital Allocators.

Hyperscalers, frontier labs and neoclouds decide the actual capital commitment. Amazon has guided to roughly $220B, Alphabet to $195B to $205B and Meta to $130B to $145B of 2026 capex. Including Microsoft, the four largest hyperscalers are on track to exceed $700B in 2026. Definitions of capex differ by company, but the direction is unambiguous. The absolute scale of capital entering AI infrastructure is still rising quickly.

Layer 3: Silicon.

Accelerators, memory and interconnect sit here. Product mix and wafer allocation can be adjusted at the margin, but structurally expanding leading-edge wafer and memory capacity takes several quarters to several years. Short-run elasticity exists, but it is not unlimited.

Layer 4: Manufacturing.

Leading-edge wafer, advanced packaging and test set the real ceiling on accelerator shipments. Even with logic and HBM ready, no finished part ships without a 2.5D packaging slot.

Layer 5: Site Infrastructure.

Power distribution, cooling, facility transformers and switchgear, and the building itself. As rack density moves into the hundreds of kilowatts, simply adding GPUs to an existing data center is reaching its limit. Electrical architecture and liquid cooling have to change together.

Layer 6: Grid.

Generation, transmission, substation and interconnection. Response time changes entirely. Large power transformer lead times have stretched into multiple years, and interconnection and energization in major data center markets take years.

Semiconductor constraints are measured in quarters and years. Grid constraints are measured in years. The reason the lower layers stay constrained longer is ultimately the difference in response time.

Subscribe now

2. Bottlenecks Do Not Disappear. They Stack.

AI infrastructure is usually explained as a sequence of shortages. GPUs were short, then HBM and CoWoS, and now power. The direction is right, but real supply chains do not hand off that cleanly.

The shorthand is that supply moved from accelerators to HBM and packaging and then to power. What actually happened is that the constraints piled up. Accelerators and the grid tightened first in 2023, HBM and advanced packaging in 2024, power and cooling in 2025, light sources in 2026.

Power and grid decide when new capacity can be turned on. Memory and packaging decide how fast accelerators already ordered can be shipped. Both constraints exist at the same time. They simply bind different things.

As of August 2026 all six layers are tight. On the shipment clock HBM supply is tightest: 2027 bit shipments are projected to grow 50 to 60% and still fall short of demand growth. Advanced packaging is also likely to stay short into 2027. On the deployment clock grid interconnection and transformers are tightest, new heavy-duty gas turbine orders run about three years to delivery, and 2030 production slots are largely booked.

Accelerators were not solved after early 2024. What changed is that accelerators no longer set their own number. How many HBM stacks and packaging slots come out determines it, and rack-level selling pulls power and cooling into the same equation. Accelerator supply is now set by the bottlenecks below it rather than creating one.

Light sources and InP substrate turned tight in mid-2026. Lead times at the major light source suppliers run past 2027, and substrate capacity is now being reserved under contracts running to 2031. What this layer gates is the pace of optical deployment rather than accelerator shipments as a whole. Where copper still reaches, the constraint does not bind.

The grid did not appear in 2026 either. Large transformer lead times were already around 140 weeks in 2023 and passed 160 weeks in 2026. The onset of each of the six is documented. The clearing dates are not: forecasts diverge too widely to fix one.

Why Power Stays Tight Longer

The reason the power constraint is likely to persist is simpler than any demand forecast. Supply response is slow. GE Vernova’s 2Q26 gas equipment backlog and slot reservations stood at 116GW against annual output targets of roughly 20GW in 2026, 24GW in 2028 and 30GW in 2030. The company has said new heavy-duty turbine orders run about three years to delivery, and 2030 production slots are largely booked.

That number is not a statement about long-run TAM. It says factory throughput is the near-term supply ceiling. Strong demand does not turn 20GW of annual output into 50GW the following year.

Workarounds Move the Bottleneck

The grid constraint is not absolute. Hyperscalers and developers are expanding behind-the-meter generation and on-site power rather than waiting for a grid connection. But as that path grows, the bottleneck does not disappear. It relocates. Interconnection scarcity falls, and scarcity in gas turbines, generators and fuel infrastructure rises.

So what an investor should look for is not the largest market. It is the point where incremental demand meets the least elastic supply.

Subscribe now

3. Scarcity Is Not an Investment Thesis

A Bottleneck Must First Become Pricing Power

A severe bottleneck does not automatically enlarge the profit pool of the industry that sits in it. Shortage is a physical condition; pricing power is an outcome of market structure.

Whether scarcity converts into supplier economics turns on four things.

1. Supply Response Time.

How quickly can capacity expand once demand rises? HBM is limited by wafer capacity and qualification, gas turbines by manufacturing throughput, transformers by electrical steel and winding capacity. The longer the response time, the longer scarcity pricing can persist. Memory, light sources, gas turbines and transformers clear this test. Module assembly and construction do not: capital and labor expand them within a few quarters.

2. Qualified Supplier Set.

The number of suppliers a customer can actually use matters more than the number that exist. If second-source qualification is easy, buyer bargaining power can be strong even with few suppliers. If requalification takes years, the customer is effectively locked in even with several suppliers on paper. Optics is the clearest split here. Transceiver assembly has dozens of competitors while the laser and substrate above it have very few, which means the verdict on this test differs by layer inside the same industry. Data center electrical construction fails it outright.

3. Substitution and Workarounds.

Can the customer use less of the component or change the architecture? Memory is the clearest case. A shortage of HBM does not force buyers to accept any price. They can lower memory capacity per accelerator or reallocate system budget to another resource. Pricing power and buyer workarounds can coexist. Among the layers that score well on the first two, memory is the clearest example of losing points here. Grid has a workaround too in behind-the-meter generation, but that path does not remove scarcity. It moves it to the turbine.

4. Contract Structure.

This determines how fast scarcity reaches ASP. Long-term fixed-price contracts delay repricing even in a shortage. Memory runs on annual contracts, but suppliers hold the stronger hand in allocation and in negotiating the following year’s price. Turbine slots go to reservation competition. In those structures scarcity converts into price. Colocation fails this test because contract terms are long, and electrical construction never engages it at all because pricing is set by competitive bidding.

The four items are a scoring frame, not a pass-fail test. Taken together, memory, light sources and the substrate above them, large-frame gas turbines, and transformers and switchgear score highest. Memory loses points on the third item, and optics loses points there too because the coupling architecture can change. Advanced packaging is easing on the first item, so its score is drifting down. Data center electrical construction is weak on the second and fourth, and colocation on the fourth. That is why the layer with the most severe bottleneck has the weakest supplier economics.

Shortage and pricing power are not the same thing.

Supply response time, qualified supplier set, substitution path and contract structure are what connect them.

What I track: Qualified supplier count · Supplier switching and qualification time · Contract duration · Repricing frequency. When those four move toward broader and longer, pricing power weakens even while the bottleneck holds.

Subscribe now

4. Pricing Power Still Has to Become Earnings

Even after pricing power is confirmed, one question remains. How far does that price amplify into earnings growth?

Volume Growth × Content per Unit × Operating Leverage

Pricing power is the ability to convert scarcity into ASP. Earnings amplification asks how far that ASP and the demand environment expand into company results through volume, content and margin.

Gas Turbines: Strong Pricing, Slower Volume

Gas turbines score very high on the first axis. Contracted demand exceeds several years of annual manufacturing capacity, large-frame suppliers are few, and customers cannot easily switch technology. But earnings amplification is tied to factory throughput. Price and mix can improve quickly; unit shipments cannot double in the near term.

Electrical Construction: Severe Bottleneck, Little Left Over

Data center electrical construction is the opposite. Labor and project capacity are short and lead times are long. But the contractor base is fragmented and large buyers can use competitive bidding. The place where scarcity is most severe is not the place where the supplier profit pool is largest.

Memory: Strong on Both Axes, with a Content Offset

HBM scores well on both axes. Supply expansion is slow, qualification is difficult, and suppliers hold the stronger hand in annual contract negotiation. At the same time, bandwidth requirements rise with each accelerator generation.

Content de-spec has to be tracked alongside price. Even with ASP rising, a lower HBM capacity per accelerator partially offsets dollar content growth. In memory, HBM price and GB per accelerator have to be read together.

Test and Burn-in: Volume Rises, Amplification Does Not

Test scores reasonably well on the first axis. Taller stacks and more complex packages add test steps and test time, so equipment demand follows. It is the second axis that binds. Tools stay in place across several generations and replacement cycles are long, so revenue arrives in steps. Volume is secured, but sustained earnings amplification is harder to reach.

Optical Components: Scarcity with Architecture Risk

Optics is an area where unit growth and content growth can appear at the same time. Laser and some upstream optical component capacity is limited, and moving from 800G to 1.6T and then 3.2T raises the dollar content of certain components.

NVIDIA’s March 2026 investment of $2B each in Lumentum and Coherent, together with multi-year purchase commitments and capacity access, shows this scarcity is a procurement issue rather than a market narrative. At the same time optics carries more architecture risk than memory. If CPO scales quickly, bandwidth can grow while dollar content in pluggable transceivers and some components falls.

Bandwidth growth is not the same as optical revenue growth.

5. Silicon: Compute and Memory

Within silicon, compute and memory run on different drivers, so the numbers that would disprove each are different.

Compute

The accelerator is still the single largest line in the AI system BOM. But as hyperscaler custom ASIC deployment grows, merchant GPUs alone no longer describe total compute economics.

Counterpoint estimates that roughly 27.8% of 2026 AI server shipments are built on custom ASICs. A separate third-party tracker, Presenc AI, estimates hyperscaler in-house accelerator deployment at roughly 1.9M units. These are external tracker estimates rather than audited shipment data.

Unit share and revenue share also move differently. Internal ASICs carry different accounting economics from merchant accelerators, so a rising custom silicon unit share does not pull merchant system revenue share down at the same pace.

What I track: Custom accelerator shipment share · Rack-level system revenue share.

Memory

HBM remains tight. SK hynix disclosed a 56.4% share of HBM revenue in the first quarter of 2026 in its US registration statement. More important is that HBM changes how wafers are allocated across the entire memory market.

HBM consumes more wafer capacity than conventional DRAM to produce the same bit. As HBM mix rises, capacity allocated to commodity DRAM falls, and DRAM pricing unrelated to AI can be affected. The current memory cycle includes this cross-market effect, not just HBM demand itself.

What I track: Next-year HBM contract pricing and the direction of negotiations · HBM capacity per accelerator. Supplier earnings leverage is strongest when price and GB per accelerator rise together.

6. Data Movement Is Taking More of the System

As compute performance rises, the cost of moving data rises with it. The larger the cluster, the more peers each accelerator has to talk to, and the higher the lane speed, the shorter the copper reach. Networking is no longer a peripheral budget attached to compute. It is becoming a variable that determines system architecture.

OIF released the CEI-448G framework document in November 2025 and launched the CEI-448G-VSR and LR projects in the first quarter of 2026. The open question is not whether 448G electrical is feasible. It is how far electrical reach can hold in the generation after that.

Scale-Up and Scale-Out Have Different Economics

Scale-up and scale-out should not be divided by the rack boundary. Scale-up is the fabric inside a tightly coupled accelerator domain, and that domain can extend across multiple racks. Scale-out connects multiple scale-up domains or clusters.

The economics differ as well. Scale-out is Ethernet-centric with a broad supplier set. Scale-up ties protocol and architecture more deeply to a compute platform. Switching cost and supplier concentration are generally higher on the scale-up side.

The Optical Bottleneck Often Sits Above the Module

Part of today’s optical scarcity shows up in upstream components rather than the complete transceiver. Lumentum reported pump laser shipments up more than 80% year on year and has expanded EML capacity repeatedly. In the 1.6T generation, 200G EML pricing is higher than the prior generation.

Moving up from the transceiver, the chain runs module assembly, laser chip, epitaxy, InP substrate. Effective suppliers thin out and substitution gets harder with each step up. Module assembly has dozens of competitors and seven of the top ten are Chinese. Laser chips come from fewer than five firms at volume, and volume supply of the 200G per lane EMLs that 1.6T needs is narrower still, concentrated in a few leading suppliers. Above that, three firms hold 80 to 90 percent of InP substrate.

The supply numbers get worse the further up you go.

TrendForce reports that lead times at the major EML suppliers have stretched beyond 2027. Consulting estimates cited in public reporting put 800G transceiver production 40 to 60 percent below demand through 2027, and 1.6T 30 to 40 percent short through 2029. At the substrate level, buyers have begun paying to reserve capacity years in advance. Epitaxy is either done in house by the laser makers or sent to a small set of specialist foundries, and MOCVD tools are export controlled, so expansion is gated by tool lead times.

This is where the second test from section 3 actually binds in optics.

The set of qualified suppliers narrows at the substrate and the light source, not at the module. Contract structure is changing at this level too. AXT disclosed in July 2026 that it signed a supply and capacity reservation agreement with Lumentum for InP substrate running through the end of 2031, with Lumentum paying a $43.5 million deposit up front and a second $43.5 million to be settled in 2028. Buying several years of capacity in advance is what happens when the part cannot be sourced on demand.

The chain above also splits by light source. EML and CW lasers sit on InP substrate and ride this chain directly. VCSEL sits on GaAs and follows a different one. Moving to silicon photonics does not remove the need for a light source, so InP demand does not disappear.

In a chain that narrows as it goes up, unit growth and content growth can appear together. But company dispersion is wide. Within the same optical upcycle, growth and margin trajectories differ sharply by supplier.

Being long optics does not mean being long every optics company.

What I track: Interconnect and optics BOM / total rack BOM · Optical transceiver count per rack · Scale-up domain size · Laser capacity additions converting into actual shipments.

7. Manufacturing Is Splitting in Two Directions

Advanced packaging is still tight, but the intensity of the shortage is easing. Industry estimates cited by TrendForce suggest TSMC’s CoWoS monthly capacity could expand to roughly 120K to 140K wafers in 2026, and that industry capacity including OSATs could approach 200K per month. The same source expects the CoWoS supply-demand gap to narrow from roughly 20% to about 10% by the end of 2026.

These are industry estimates rather than official TSMC monthly capacity guidance, and estimates published at the same time point the other way: 2027 CoWoS demand more than doubling in wafer terms and leaving a 10 to 20% shortfall even at industry capacity near 200,000 wafers a month. A TSMC executive said in August 2026 that capacity is now close to demand and that the bottleneck is moving upstream to materials such as ABF substrate. Either way the direction is the same. As a bottleneck eases, volume growth and mix matter more than pricing upside, and what remains binding moves further up the chain.

Test moves the other way. As HBM stacks get taller, package complexity increases and optical components move into the system, the number of test steps and total test time can rise. Test economics become more sensitive to process complexity and test intensity than to wafer volume.

What I track: CoWoS supply-demand gap · Test time per package or stacked device.

8. Power Is Now the Deployment Clock

The layer that most tightly constrains the turn-on timing of new AI capacity is power and grid. GE Vernova said new gas turbine order pricing in the first half of 2026 rose further from prior levels. In transformers and switchgear, data center developers and utilities compete for the same manufacturing capacity.

Wood Mackenzie estimates cited in public reporting see the US data center electrical equipment market expanding from roughly $20B in 2026 to $65B by 2030. Over the same period US data center capacity is projected to grow from roughly 24GW to about 100GW.

Revenue growth alone is not enough in this market. What tells you whether scarcity is holding is backlog divided by annual manufacturing capacity and equipment lead time. When both start falling consistently, pricing power starts weakening with them.

9. Thermal Is an Execution Story

Cooling and power management are past the stage of having to prove demand. Vertiv reported second quarter 2026 revenue of $3.274B, up 24%, with adjusted operating margin reaching 22.6%.

The question in this layer is not whether the orders exist. It is how fast backlog converts into revenue, and whether margin holds through that conversion.

Space and construction are different again. Shell construction and electrical work face severe shortages too, but the contractor base is fragmented. Colocation reprices slowly because of long-term contracts. Even inside the same physical infrastructure layer, how severe the bottleneck is and whether it leaves any profit have to be assessed separately.

What I track: Backlog conversion · Incremental margin · Lead-time normalization.

10. Demand Is the Reset Condition

Applications and frontier models should not be judged with the scarcity framework. This layer has no physically fixed supply ceiling like an HBM wafer or a transformer factory. What matters is monetization.

Hyperscaler capex is on track to exceed $700B in 2026. Sustaining infrastructure spending at that level requires AI revenue, cloud demand, advertising monetization and enterprise productivity to eventually justify the capital intensity. Frontier lab revenue is only one part of that. Hyperscalers carry a far larger cloud, advertising and software cash flow base.

So I do not simply compare frontier lab revenue with capex. The more useful question is whether AI monetization is expanding in the same direction as infrastructure spending.

Demand reset condition: if capex guidance from the major hyperscalers is cut for two consecutive quarters, the demand map has to be redrawn before the supply map.

11. Two Calls and One Principle

The two judgments below are the base case the current data supports. If the conditions change, the calls change with them.

Call #1: Power and Grid Remain the Dominant Constraint on New Capacity Through 2027

My base case is that the dominant constraint on the turn-on timing of new AI capacity stays with power and grid at least through 2027. That does not mean the memory and advanced packaging shortages are over. They continue to gate the shipment clock. The difference is response time.

What I track: Gas equipment backlog / annual production capacity · Transformer lead time · Major data center market interconnection wait time.

What breaks the thesis: two or more of those three indicators improving materially for two consecutive quarters, or behind-the-meter generation becoming a standard deployment model so that grid connection no longer sets turn-on timing.

Call #2: Data Movement Takes a Larger Share of AI System Economics Through 2028

My second base case is that data movement takes a larger share of AI system economics through 2028. Cluster size is growing, and copper reach shortens as electrical lane speed rises. Larger scale-up domains and more high-speed connectivity follow.

This should not be read as a simple optics bull case.

If CPO is adopted quickly, the same bandwidth can be delivered with lower optical dollar content.

What I track: Interconnect and optics BOM / total system BOM · Transceiver count per rack · Scale-up domain size · Optical component capacity converting into shipments.

What breaks the thesis: scale-up domain size flattening for two consecutive generations, 448G-class electrical connectivity achieving longer reach than expected and delaying optical penetration, or CPO cost reduction moving so fast that bandwidth rises while optical dollars per system fall.

Principle: Bottlenecks Do Not Determine Profit Pools. Market Structure Does.

This is a structural principle rather than a forecast for any particular year. Where the bottleneck sits does not determine who keeps the profit. Qualified supplier set, switching time, substitution path, contract duration and repricing frequency do.

Memory and electrical construction make the point. Both can be in short supply. But memory has a limited supplier and qualification path, and suppliers hold the stronger hand in the following year’s price negotiation. Electrical construction has a broad supplier base and allows competitive bidding. The same shortage produces entirely different margin outcomes.

Bottom Line

AI infrastructure is neither one trade nor one bottleneck. Constraints exist across several layers at once, and the dominant constraint migrates toward the slower physical layers over time.

As of 2026, power and grid have begun to govern the deployment clock for new capacity. HBM and advanced packaging continue to gate the shipment clock. Data movement is likely to take a larger share of system economics.

But those three facts do not by themselves select an investment. Scarcity must become pricing power. Pricing power must become earnings.

What decides that conversion is not the shortage headline. It is market structure.

I will keep publishing analysis and articles at this level, and I am open to collaboration proposals around that work. Any form of collaboration is welcome. Please reach me at

research@damnang.com

Sources & Notes

Company results use official IR or SEC filings where available. Industry figures use public reporting and third-party estimates. Capacity and market-size numbers distinguish company guidance from third-party estimates.

1. NVIDIA, fiscal 2027 Q2 results (revenue $96.2B, Data Center $89.0B, gross margin 75%).

2. NVIDIA, fiscal 2027 Q1 CFO commentary (Data Center compute $60.4B, networking $14.8B).

3. GE Vernova, 2Q26 results 8-K (orders $24.2B, backlog $176B, gas equipment 116GW, capacity plan).

4. Reporting on GE Vernova gas turbine backlog and data center related orders.

5. Vertiv, 2Q26 results (revenue $3.274B, adjusted operating margin 22.6%, guidance raised).

6. Lumentum, fiscal 2026 Q4 results and conference call (revenue $1.006B, systems $357M, pump laser, OCS outlook).

7. Lumentum, August 2026 Deutsche Bank technology conference summary (copper reach and optical penetration, OCS demand).

8. OIF, Next Generation CEI-448G Framework Document released (November 2025).

9. OIF, CEI-448G-VSR and CEI-448G-LR projects launched at the Q1 2026 meeting.

10. NVIDIA, strategic partnership with Lumentum and $2B investment (March 2026).

11. NVIDIA and Coherent, strategic partnership and $2B investment (March 2026).

12. Comparison of Lumentum and Coherent fiscal 2026 Q4 results (Coherent revenue $2.05B, up 34% year on year).

13. SK hynix, US registration statement (56.4% share of HBM revenue in 1Q26, citing IDC).

14. TrendForce, CoWoS supply-demand gap outlook and capacity expansion plans.

15. Enterprise SSD contract pricing and segment revenue (1Q26, citing TrendForce).

16. DRAM and NAND contract price outlook (citing TrendForce).

17. Transformer lead times and PJM interconnection timelines.

18. US data center electrical equipment market size and capacity outlook (citing Wood Mackenzie).

19. Aggregated hyperscaler 2026 capital expenditure guidance.

20. Custom ASIC share of AI server shipments and growth (Counterpoint).

21. Hyperscaler in-house accelerator deployment estimate.

22. Frontier lab annualized revenue reporting (revenue definitions differ by company).

23. AXT, 8-K disclosing an InP substrate supply and capacity reservation agreement with Lumentum (July 29, 2026).

24. TrendForce, AI data center driven laser shortage and EML lead times beyond 2027.

25. InP epitaxy outsourcing and MOCVD export controls in the laser supply chain.

26. Sumitomo Electric raising the scale of its InP substrate expansion (JPY 18 billion).

27. InP substrate supplier concentration.

28. 2027 CoWoS demand and capacity estimates, with a 10 to 20% shortfall.

29. TSMC executive on CoWoS capacity approaching demand and the bottleneck moving to ABF substrate (OCP APAC, August 2026).

30. TrendForce, 2027 HBM bit shipments up 50-60% and still short of demand growth.

31. GE Vernova lead times on new gas turbine orders and the state of 2030 production slots.

NVIDIA disclosed NVHBM on August 26, 2026. It said it would put a custom memory controller into the HBM base die and let multiple memory providers supply the same NVHBM specification. Versus standard HBM4E it cited up to 30% higher stack bandwidth, up to 15% lower HBM power and up to 25% more XPU compute die area.

People outside the semiconductor industry sometimes read the name and assume NVHBM is a new form of HBM.

It is not.

The industry calls the HBM we normally refer to standard HBM, or sHBM, and calls the products whose base die is tailored to a customer’s requirements cHBM, or custom HBM. Research and development on cHBM has been under way for years. NVHBM is simply the cHBM NVIDIA uses.

The reason NVHBM deserves attention is not that it is technically special.

It is that NVIDIA defines its own cHBM specification, namely the controller and interface that sit in the base die, and intends to have multiple memory suppliers build to that same structure. In other words, the domain memory vendors used to design together with their customers moves wholesale into NVIDIA’s platform layer. That is where its significance lies. Section 4 onward covers this in detail. First, though, we look at why cHBM emerged and what it means for memory vendors.

Subscribe now

2. The Faster HBM Gets, the More the XPU Pays

HBM has raised bandwidth in two ways: widening the interface between XPU and HBM, and running each signal faster. The interface went from 1,024-bit in HBM3E to 2,048-bit in HBM4, and pin speed keeps climbing.

The problem is that HBM does not bear the cost of higher bandwidth alone. A wider interface requires more PHY and I/O circuitry on the XPU as well, and consumes more die edge and more interposer routing. Higher signal rates add power and signal-integrity burden on top.

In an AI accelerator this cost matters more. The XPU’s leading-edge silicon is an expensive resource that should go to compute and cache wherever possible. Yet the more HBM bandwidth rises, the larger the share of that area and power budget the memory interface takes.

So the problem after HBM4 is not solved by making DRAM itself faster.

What is needed is

an architecture that delivers the same bandwidth using less XPU area and power.

That is where the value of an advanced-logic base die and a custom interface comes from.

Subscribe now

3. cHBM Reduces That Cost While Creating a New Source of Revenue and Profit

The main disclosed direction for cHBM is to move part of the memory-related logic out of the XPU and into an advanced-logic base die, and to redefine the XPU-to-HBM interface to fit the system. That frees some of the area the HBM PHY and controller occupied on the XPU, and lets the recovered silicon and power budget go back to compute or cache.

For memory vendors this creates a new value pool. In standard HBM, DRAM die, stacking, test and qualification accounted for most of the product value. In cHBM, base-die design, controller and PHY IP, verification, NRE and customer-specific optimization can be added on top.

Micron’s stated expectation that a customized HBM4E base logic die will carry a higher gross margin than standard HBM4E points the same way. cHBM is not simply faster HBM. It is a product through which memory vendors can sell more engineering value.

Subscribe now

4. NVHBM Can Redistribute cHBM’s Value Capture Toward NVIDIA

Throughout this article, custom HBM whose architecture is designed anew for each customer is called bespoke cHBM, and the model in which a platform owner such as NVIDIA sets the spec and multiple suppliers build the same structure is called platform-defined cHBM.

In bespoke cHBM, base-die architecture and qualification can differ by supplier. Once controller, PHY and base die have been designed with one memory vendor, switching to another requires redesign and revalidation. That switching cost is an important reason memory vendors can defend custom design premium and customer relationships.

NVHBM changes this structure. Instead of memory vendors building different cHBM architectures with each customer, NVIDIA defines the controller and interface and multiple memory providers supply the same NVIDIA implementation.

That also changes where the new logic value in an HBM stack accrues. In bespoke cHBM, a memory vendor can go deeper into base-die design, controller, PHY and customer-specific logic and capture proprietary design value. Under NVHBM, NVIDIA defines much of the architecture, so memory vendor differentiation is likely to shift toward DRAM performance, stacking, yield, power and manufacturing execution.

Multi-sourcing reinforces the shift. When several suppliers meet the same NVHBM specification, NVIDIA can qualify suppliers against more common criteria and allocate volume accordingly.

That does not mean memory vendors become fully interchangeable or that prices automatically fall. HBM still differs meaningfully by supplier in capacity, yield, speed, power and thermal behavior, and supply itself remains constrained.

Even so, a common architecture works in the direction of lowering supplier-specific switching barriers. The net effect is that NVHBM increases NVIDIA’s influence over custom memory architecture and supplier selection, and can move part of the design value memory vendors could capture in bespoke cHBM toward the platform owner.

Subscribe now

5. What NVIDIA Is Optimizing Is Not HBM but the Whole AI System

Taken separately, density despec and NVHBM look like HBM optimization. The scope NVIDIA is drawing is wider than that: binding compute, memory and interconnect into a single AI factory architecture rather than treating them as separate components.

Density despec lowers memory capacity per accelerator but lets a constrained DRAM supply produce more HBM stacks. All else equal, moving from 12-Hi to 8-Hi raises the number of stacks buildable from the same DRAM die output by a theoretical factor of 1.5. At the same time, demand for base-die units, one per stack, rises.

In NVHBM, NVIDIA directly defines the architecture between XPU and HBM. Outside that, NVLink and NVSwitch handle Scale-Up while Spectrum-X and InfiniBand handle Scale-Out. NVIDIA has added Scale-Across, Context Memory and BlueField-4-based Scale-In to frame the AI factory as five infrastructure pillars. As rack and data center scale grow, optical connectivity grows in importance alongside them.

Add NVLink Fusion and NVIDIA does not need to build every piece of compute silicon itself. Custom XPUs and CPUs are allowed, while memory, the scale-up fabric and the MGX rack architecture still connect into the NVIDIA platform. Amazon Annapurna Labs being named the first NVHBM collaborator, with NVLink Fusion support signaled from Trainium4, shows this strategy is aimed at custom XPUs beyond NVIDIA’s own GPUs.

What NVIDIA is expanding is not just GPU share but the scope of the AI system whose architecture it defines. From the GPU out to HBM, rack-scale interconnect, networking, context memory and infrastructure access, that boundary keeps widening. NVHBM is one step in bringing the memory layer inside the NVIDIA platform.

Subscribe now

That is how the market reads NVHBM today: NVIDIA takes the spec and keeps widening the scope it defines. Most commentary stops here.

So are memory vendors simply losing ground? No.

This is not the last round. Memory vendors are already preparing for the next one, and in that round there is one position left where what NVIDIA has taken can be won back. It is a domain that cannot be pinned down in a specification, which is exactly why it resists commoditization. Look at where Samsung and SK hynix are putting people and money right now and the direction becomes visible.

The same shift also does not land on all three memory vendors the same way. Set a few conditions, run the numbers per accelerator, and a variable emerges that moves profit far more than design ownership itself. How sensitive that variable is, and how far down the value chain the change carries, is what the rest of this analysis quantifies.

The era of reading HBM through bit growth is ending. What to watch and what to verify in the next cycle starts here.

6. Memory Vendors Respond by Splitting Volume and Design Value

Read more

This material is general research opinion based on public information and is not investment advice tailored to any individual. Future contracts, capacity targets, ARR and secured power are conditional figures, and actual outcomes may differ depending on financing, permitting, utility schedules, supply chains, customer acceptance and demand.

A neocloud, put simply, is a company that rents out GPUs for AI.

AI companies need large scale compute to build models, but securing the latest GPUs and building data centers takes enormous capital and time. Neoclouds build the power, the data center, the NVIDIA GPUs, the high speed network and the operating software first, then rent that stack to customers. Instead of building their own AI factory, customers buy compute capacity that is ready to use.

The reason to look at this industry now is that neoclouds are growing from a stopgap for temporary GPU shortages into an independent supply layer of AI infrastructure.

On its FY27 second quarter call, NVIDIA projected that installed capacity at its neocloud partners would grow from roughly 3 GW at the end of 2025 to 8 GW at the end of 2026. Beyond AI startups and enterprises, hyperscalers that operate their own data centers are also using AI clouds to supplement capacity they lack.

This layer may also persist after GPU supply normalizes. GPU generations turn over quickly, but grid connections, substations, cooling and data center sites can be reused by the next generation of equipment. Even when customers change, a standardized NVIDIA cluster can be redeployed to other AI workloads.

This article is a technology and investment guide for anyone considering the three listed neocloud names, CoreWeave, Nebius and IREN.

The three sit in the same industry, but how they make money and what risks they carry are different.

How much of the power and data center they own directly, what kind of capital they use to secure GPUs, and whether the numbers they announce are still secured megawatts or capacity that has already passed customer acceptance all change the investment call.

The article first explains what a neocloud is and what a megawatt means, then compares the technical strengths, economics, capital structure and execution risk of the three companies, and finally sets out how to approach each name at current prices.

Subscribe now

A neocloud rents out AI compute, not just GPUs

What the customer buys is not the GPU itself but an AI computing environment that is ready to use. A neocloud bundles power, the data center, thousands of NVIDIA GPUs, a high speed network and operating software, and rents that bundle out.

Capability is not determined by GPU count alone.

Thousands of GPUs have to behave as a single computer. If the network congests, if cooling wavers, or if the software that splits the work stalls, even expensive GPUs fail to earn properly. What matters is less how many GPUs a company holds than how reliably and how quickly it finishes customer jobs.

Where general clouds such as AWS, Azure and Google Cloud sell storage, databases and business software as well, neoclouds concentrate on AI compute. They can install the latest GPUs faster, but capital intensity is high and dependence on a small number of large customers is easy to fall into.

Subscribe now

A megawatt is the size of the power a data center can draw

MW (a megawatt) is the amount of power a data center can use at a point in time. One MW is one million watts. Used continuously for a year, that consumes 8,760 MWh. GPU models keep changing, but grid connections and cooling capacity do not expand easily. That is why neoclouds describe the scale of their business in megawatts.

The same megawatt figure can be measured on different bases.

Facility MW is the power the whole site draws, while IT MW is the power that actually reaches GPUs, CPUs, storage and the network. Cooling and power conversion take the rest, which creates the gap.

Note that if a company does not state which basis it used, two companies cannot be placed side by side. In other words, what matters is less the megawatt figure itself than the basis and the method used to compare.

MW 101

Moving from secured power to a completed data center, to IT power delivered to servers, to capacity that has passed customer acceptance, the megawatts that can actually be used shrink at every step. What remains then meets a contract and becomes operating ARR, and passes through utilization and costs to become shareholder cash flow. The further along the chain, the smaller the number but the higher the certainty that it turns into revenue.

CoreWeave leads on installation and bring-up speed and on large scale production operating experience.

Nebius aims to raise revenue per MW by selling software alongside compute.

IREN controls its own power and land, but still has to complete facilities on schedule and pass customer acceptance.

Subscribe now

Secured megawatts and earning megawatts are not the same thing

The megawatt figures companies announce are best read in three stages. The first is power secured so that it can be developed at some point. The second is IT power that will actually be delivered to the data center and the GPUs. The third is operating power that has passed customer acceptance and started earning. The earlier the stage, the larger the number and the greater the uncertainty.

The megawatts the three companies announce also point to different stages.

Placing the three companies’ megawatts on one line therefore risks a wrong read of how far each business has actually progressed.

When secured power actually arrives differs by site and by utility contract. Rather than relying on a target year, three things are worth checking.

First, when the utility contract was signed and what delivery start date it specifies.

Second, whether the site is already receiving electricity or is still building its substation.

Third, whether the quarterly increase in active power a company reports is running at a pace consistent with the target schedule.

Dividing the quarterly increment by the remaining period, as with CoreWeave adding roughly 500 MW in a single quarter, gives a rough sense of whether the target is achievable.

Subscribe now

What NVIDIA has actually committed to the neoclouds

As described above, a neocloud has to commit large capital to power, buildings, cooling and GPUs before any revenue starts. Several years pass between securing power and customer acceptance, and during that period there is no revenue while interest and depreciation accrue.

NVIDIA intervenes in that window in three ways. It buys compute capacity from the neoclouds directly, it connects financial institutions to widen funding channels, and it attaches guarantees to some projects. The structure is one where NVIDIA buys back services run on the very GPUs it sold. For the operator, a minimum level of demand exists even during the construction period with no revenue, and that contract supports borrowing at a lower rate.

The market has taken this as a sign that the funding problem for neoclouds has been solved.

It is therefore worth checking, against the filings, how much NVIDIA actually guaranteed, to whom, and on what terms.

In the 10 Q filed on 26 August, NVIDIA’s maximum guarantee exposure was $108.5B.

Of that, $105B relates to the roughly 4.25 GW project SB Energy is developing in Ohio, connected to an OpenAI affiliate, and is unrelated to the neoclouds. AI cloud related guarantees total $3.5B.

That figure, however, is disclosed as an aggregate guarantee for select AI cloud partners, and public disclosure alone does not establish that it is allocated to CoreWeave, Nebius and IREN.

Separately from guarantees, NVIDIA agreed to buy cloud capacity from these operators directly. The commitment totals $36B, typically over six years. Where a guarantee is a ceiling against default, this is a capacity purchase commitment that converts into revenue when the conditions are met. That said, if operators sell that capacity to other customers, NVIDIA’s purchase obligation falls accordingly, so the full $36B is not fixed revenue.

The third form of support is the funding channel. On 10 August, NVIDIA announced a compute financing platform with Apollo, BlackRock, Blackstone, Brookfield, Goldman Sachs and KKR aimed at mobilizing over $500B. The structure supplies capital against AI infrastructure as collateral, and the market read it as a sign that the neocloud funding constraint was easing.

It is, however, a memorandum of understanding with large financial institutions rather than committed capital, and individual projects still have to be underwritten separately. NVIDIA may support the residual value of some GPUs, but there is no disclosure guaranteeing the price of all equipment.

Subscribe now

Even with NVIDIA’s help, power and bring-up remain each company’s own work

The risk NVIDIA has removed is concentrated in funding and early demand. Bringing power in, completing the data center, stabilizing the GPUs and passing customer acceptance all remain with the operator. This is where results diverge even when the three companies buy the same NVIDIA equipment and receive the same support.

The first source of that remaining risk is equipment delivery. NVIDIA stated in its most recent 10 Q that Rubin and Blackwell supply is constrained and that the complexity of data center systems can cause production delays and lower yields. Even with funding secured, racks arriving late push the schedule back by the same amount.

Revenue does not begin the moment the racks arrive either. A new generation cluster has to stabilize power and cooling, isolate faulty nodes, and verify network and storage before customer workloads confirm performance and stability. During this bring-up period a gap opens between installed MW and the MW a customer can actually use, and the revenue start date slips by that gap.

Bring-up time differs by company and shrinks from batch to batch within the same company, because the failure modes and inspection procedures found in the first cluster can be reused in the second and third. That repeated experience is what separates how fast secured power turns into revenue.

So where do the three neoclouds stand now, and what should be watched most closely?

That covers the basics of what a neocloud is.

Below, the same standards are applied to the three companies. The article then sets out why CoreWeave’s RPO, Nebius’s ARR and IREN’s contracted ARR cannot be compared on the same yardstick, breaks down what survives beyond a single GPU generation across five axes, and closes with a detailed investment view and approach for each name.

Read more

I have been analyzing Marvell closely since the beginning of this year and have shared a positive view across several articles.

To start with the conclusion, I remain very positive on Marvell.

This piece looks in detail at how far the five checkpoints from Part 2 have been validated, which parts can still remain as upside for the stock, and where the valuation stands. For readers who want a fuller picture of the company itself, the earlier articles below are the place to start.

Disclaimer

This note is a personal research piece written for information and industry analysis. It is not a recommendation to buy or sell any security. The author may hold positions in the securities discussed and may transact in them in the future. Revenue estimates, valuation, scenarios, and architecture interpretations that are not attributed to company guidance or public disclosure are the author’s judgment and may differ from actual outcomes. The system architecture read-through connecting NVIDIA, SK hynix, and Marvell does not imply any disclosed three-party co-development agreement.

Subscribe now

1. Part 2 checkpoints: four of five passed

Part 2 laid out five checkpoints for the May 27 print. Four have passed and one is partly confirmed. The largest change is that the Interconnect earnings contribution arrived faster than expected.

Part 2 update

The upside case at the time centered on next-generation Custom Silicon ASP. In practice the FY27 earnings revision came from Interconnect first. The larger Custom growth contribution remains ahead in FY28.

Subscribe now

2. FY27 = Interconnect, FY28 = Custom

Marvell FY26 revenue was $8.195B.

The current company outlook is roughly $11.5B for FY27 and roughly $16.5B for FY28. Incremental revenue is about $3.3B in FY27 and a further $5.0B in FY28.

The FY27 Data Center growth guide is about 50% and the Interconnect guide is above 70%. The Q1 investor presentation put Custom growth above 20% in FY27 and above 2x in FY28. FY27 earnings leverage sits with Interconnect, while the FY28 growth mix shifts toward Custom.

Subscribe now

3. Optical, Interconnect and Switching: the most de-risked FY27 driver

Read more

Rubin Ultra’s HBM configuration is being reviewed downward, from HBM4E 12-Hi toward HBM4 8-Hi. Supply constraint is the direct cause, but supply alone does not make the choice work. It works because a wider scale-up domain and software tiering absorb the loss of per-GPU memory capacity at the system level.

That direction leads to optics and memory disaggregation. A Nature Electronics review published on August 20 lists an SK hynix researcher as a corresponding author. Marvell is co-developing scale-up networking and silicon photonics with NVIDIA, and CXL-based CMM-Ax with SK hynix.

Disclaimer This article is written for informational purposes and does not recommend buying or selling any security. The 8-Hi configuration for Rubin Ultra is unconfirmed information based on industry checks, and the final specification may change. The yield and revenue figures in this article are scenario sensitivities, not company guidance or shipment forecasts.

1. The stack count fell because the GPU domain grew

On August 4, TrendForce said NVIDIA is evaluating several lower-capacity configurations alongside 12-Hi HBM4E and that the final specification has not been set. The Information reported prototype testing of 192GB and 256GB configurations, and SemiAnalysis sees the main SKU moving down to HBM4 8-Hi 192GB while compute performance holds and memory bandwidth rises slightly.

As someone who has covered this issue before, what I hear from the field is that the major memory makers are now running daily meetings with the customer on the basis of HBM4 8-Hi as the main Rubin Ultra configuration and are entering spec decisions on that footing. Some sources mention a 4-Hi configuration, but there is no verifiable basis for it, so it is not treated here.

All of this points to one thing.

On Rubin Ultra, pushing HBM density as high as it will go is no longer the only path to system optimization.

Why is this happening?

The first reason for the spec change is supply.

DRAM is likely to stay tight through 2027, and HBM4E still carries schedule uncertainty in qualification at the performance level NVIDIA is asking for. Twelve-layer stacking also costs more in throughput and yield than eight.

The second is system structure.

The field view is that on Rubin Ultra, bandwidth and data movement are becoming a larger constraint than memory density. In other words, the system has entered a regime where improving how data moves contributes more to performance than adding capacity.

Package-level constraints compound this.

Adding HBM stacks around the GPU raises package area and interposer-edge I/O cost. Raising the layer count inside the same stack instead increases stacking process complexity, yield loss, thermal load and package complexity. The higher HBM density goes, the more the system has to pay for each additional unit of capacity.

A wider scale-up domain, by contrast, lets some of that capacity move to peer HBM and to memory tiers outside the package. Where the gap narrows between the value of additional local capacity and the package cost of obtaining it, improving data movement can serve system efficiency better than pushing memory density further.

8-Hi is a response to supply constraint. What makes it workable is a system structure that leans on scale-up bandwidth and memory placement instead of pushing local memory density higher.

The software and memory placement techniques that keep performance intact at HBM4 8-Hi 192GB were covered separately in “What Does Rubin Ultra’s 8-Hi HBM Mean?” on August 10. Details are here.

I see two changes following from this. Optics widens the physical reach of the NVLink domain, and memory disaggregation narrows the range of memory capacity that must sit inside the GPU package.

SK hynix and NVIDIA each gave their own reasons for the CPO paper and for the $2B investment in Marvell. The public statements from NVIDIA and Marvell cite NVLink Fusion, custom XPU, scale-up networking and silicon photonics.

What I do is read both moves as signals from the same system-level data movement problem. NVIDIA, SK hynix and Marvell: the sections below look at the picture the three are drawing, and at what this change could mean for memory makers and for HBM.

2. From NPO to CPO: optics moves from rack-to-rack links toward package I/O

The difference between NPO and CPO is how close the optical engine sits to the ASIC. NPO keeps the optical engine outside the XPU or switch package but places it as close as possible on the board. Marvell cites the advantage that optics can be adopted without redesigning the XPU package.

CPO puts the photonic die and the electronic die inside the same package or interposer. That shortens the distance high-speed electrical signals travel outside the package, which helps bandwidth density and energy efficiency, but it raises the burden of thermal management, optical alignment, package yield and reliability.

SemiAnalysis reads the optical technology used in Rubin Ultra NVL576 as an NPO structure, and my previous article was written on that basis. Public disclosure and industry reporting should be separated here, though. NVIDIA has disclosed that NVL576 binds eight racks of 72 GPUs into a single 576-GPU NVLink domain and uses direct optical connections between racks.

NVIDIA’s public technical material does not state whether the packaging topology of that optical link is NPO or CPO.

What it does provide is the technical basis for why optical I/O has to move closer to the package after NPO, and how the next step leads to CPO and the photonic interposer.

For a detailed discussion of the technological evolution and market dynamics of NPO and CPO, please refer to the article below.

The Nature Electronics review with an SK hynix corresponding author sets out the physical background of this shift. In the paper, compute throughput has tripled roughly every two years, while over the same two-year cycle interconnect bandwidth advanced only about 1.4-fold. Even when HBM lifts bandwidth inside the package, resistive loss and capacitive loading on copper traces grow again once data crosses the board and cables. At high rates, equalization, retimers, DSP and FEC correct for that while adding power and latency.

The integration roadmap in the paper points the same way. From pluggable and on-board optics through 2.5D CPO, 3D TSV, hybrid bonding and monolithic integration, the optical conversion point moves closer to compute at each step. 2.5D is the compromise between manufacturability and performance, while 3D delivers higher bandwidth density and lower energy per bit at the cost of thermal and bonding yield.

On that reading, the NPO reported for NVL576 is better understood as an intermediate step that lowers package redesign and serviceability burden, rather than the end of the optical transition. The move to CPO gains economic footing as bandwidth density and I/O power become the binding constraints.

The energy and bandwidth density figures are the representative values the paper gives for each integration method. The pluggable column is on a transceiver basis.

The significance of this paper is that a technical review with a memory maker involved extends the AI system bottleneck from HBM bandwidth itself to data movement between compute and memory, and sets out a direction that pulls optical I/O closer to the package.

I read this as the key technical inflection in the memory and optics roadmap that SK hynix, Marvell and NVIDIA are drawing.

3. Disaggregation: extending local HBM capacity into a system memory domain

Local HBM remains the fastest memory tier. On the field checks used in my earlier work, Rubin’s local HBM bandwidth is about 21 to 22TB/s, while NVLink 6 delivers roughly 3.6TB/s of GPU-to-GPU bandwidth per GPU. Another GPU’s HBM does not replace local HBM. What changes is how much of the weights and KV cache must sit in one GPU’s HBM.

NVL576 implements that change inside the scale-up domain first. Active weights and hot KV stay in local HBM, while distributable weights and KV spread to peer HBM. Software hides remote memory latency by prefetching what is needed or by sending the token to the GPU that holds the data. One step further and capacity itself moves outside the GPU package, which is memory disaggregation.

This is not a structure that removes local HBM. Latency-sensitive data stays in HBM, and only data that needs capacity and reach moves to a larger memory tier.

The long-term structure in the Nature Electronics review takes this further. Fig. 4 shows XPU pool and memory pool separated and linked by a photonic interposer. The paper does not treat this as a finished architecture. It names an optical memory interface that preserves coherence while lowering latency, low-power photonic switching and multi-hop signal regeneration as problems still to be solved. The drawing is therefore a research direction for the optical architecture that separating memory and compute would require, not an SK hynix commercial product roadmap.

XPU pool and memory pool are separated and linked by a photonic interposer and optical fibre. This is the long-term direction the paper sets out, not a commercial product roadmap.

Subscribe now

SK hynix’s shipping products move on electrical disaggregation first. CXL pooled memory lets multiple hosts share memory, and CMM-Ax attaches compute to CXL memory so that long-context inference can handle a KV cache larger than GPU HBM. Disclosed in August 2026, CMM-Ax is a co-developed product combining Marvell Structera A with SK hynix DRAM and software stack. The actual link between SK hynix and Marvell shows up first in the CXL memory tier, not in optical memory.

This widens the scope of SK hynix’s business from the DRAM die itself to a broader memory architecture. HBM and custom base die sit in the local fast tier, CXL and CMM-Ax in the external capacity tier, and the photonic memory pool in the paper in a longer-dated optical tier.

Disclosed products and one paper are not enough to confirm a transition into a system-level memory vendor, but the direction is visible: the scope that has to be co-designed with the customer widens from the memory die to the controller, base die, packaging and memory placement. If that structure does reach commercial deployment, the value-added and customer stickiness SK hynix captures could exceed what selling bits alone provides.

Marvell is extending its portfolio into the next layer. It secured Photonic Fabric through the Celestial AI acquisition in February 2026, and at FMS in August it disclosed a structure in which multiple XPUs and racks reach a shared warm KV cache tier of up to 32TB over an optical fabric within 50m. The 32TB, the 50m and the 2 to 3x token throughput are vendor targets set by Marvell. They are not figures that indicate commercial deployment.

What deserves attention here is that the optical structure Marvell presents and the drawings in this Nature Electronics review share the same layer structure.

Fig. 4c of the paper shows a multi-chip module cross-section with ASIC, CPU, HPU and HBM chiplets placed together on a photonic interposer with embedded optical waveguides.

The Photonic Fabric Module Marvell obtained through the Celestial AI acquisition is a 2.5D package that places an ASIC, HBM cache and DDR5 channels together on an active photonic interposer.

On Marvell’s disclosed specification it supports up to eight DDR5 DIMMs, 72GB of HBM cache and 7.2Tbps of optical bandwidth. If Fig. 4b of the paper is a structure that links XPU pool and memory pool through a photonic interposer, Marvell’s memory module and PF-NIC configuration is closer to an implementation of that structure at module level, arriving first.

The problem definitions overlap as well.

The paper points to I/O density at the die periphery limiting channel count and routing flexibility in 2D configurations, and in Fig. 4d it sets out vertical connection between stacked PIC and EIC through optical TSVs. Marvell instead takes optical I/O out from the middle of the die rather than the die edge. The implementation differs, the constraint being solved is the same.

That similarity is an observation at the structural level. The inclusion of Celestial AI’s Photonic Fabric in the paper’s table of industrial platforms is verifiable, but there is no announcement that SK hynix and Marvell are co-developing in the optical memory space. The confirmed contact points between the two remain custom HBM and CMM-Ax. Sharing a structure and having a joint product are two different things.

In parallel, NVIDIA and Marvell announced co-development of NVLink Fusion compatible scale-up networking and silicon photonics in March 2026, and NVIDIA invested $2B in Marvell. Marvell sits at the point where optical I/O for XPU scale-up and CXL-based memory disaggregation meet.

NVIDIA offsets local HBM density with system-level scale-up, SK hynix extends the memory tier outside HBM, and Marvell supplies the electrical and optical interconnect both structures require. The link between the three companies is built out of that division of roles. Moving right, verifiable evidence thins out and the content moves closer to a research direction.

4. HBM implications: bandwidth, yield and memory hierarchy matter more than stack height

If the 8-Hi transition is confirmed as the final specification, HBM capacity per GPU clearly falls.

Against the same GPU shipment volume, that is a mix down in HBM content. Under the current supply constraint, though, the per-GPU bit decline cannot be applied directly as a decline in HBM market revenue. Lowering stack height raises the number of stacks that can be built from the same DRAM and stacking capacity, and NVIDIA can absorb that into additional GPU shipments.

HBM does not lose its role. Local HBM stays the fastest tier, and part of the additional capacity spreads into peer HBM, CXL memory and optical shared memory.

In the sensitivity used in my earlier work, moving from 12-Hi to 8-Hi gives up to a 1.5x effect from stacking time and a 1.084x improvement in stack yield under a 98% per-core-die yield assumption.

Multiplying the two puts the effective output ceiling at about 1.63x. Assuming all of that volume is absorbed into additional NVIDIA GPU shipments, total HBM revenue lands at about 81.5% of plan if 8-Hi is priced at 50% of the planned HBM4E, and about 98% at 60%. These are sensitivities to stack count, not shipment forecasts.

The competitive variables change too. In the regime where 12-Hi and 16-Hi stack height was itself the axis of differentiation, high-stack qualification and stacking technology carried a large premium. If the life of 8-Hi extends, yield, capacity, supply stability and base die functionality carry more weight. SK hynix expanding custom base die and a CXL-based memory tier together sits against the same change.

For Marvell the read-through runs the other way. Keeping accelerator utilization intact while lowering local HBM capacity raises the importance of scale-up bandwidth, optical reach and external memory tiers. That is why NVLink Fusion and silicon photonics work with NVIDIA, CMM-Ax with SK hynix, and Photonic Fabric through the Celestial AI acquisition connect inside one portfolio.

As optics moves closer to compute, from pluggable through NPO, CPO and the photonic interposer, supply chain value moves with it. Volume growth in optical engines and laser sources comes first, and silicon photonics PICs, drivers and TIAs, fiber coupling, 2.5D interposers and 3D bonding gain weight after that. If CPO and optical memory reach high-volume production, the beneficiary set is not limited to light source makers but widens across photonics and advanced packaging.

Subscribe now

This is why I keep calling for a second round in optical investing, and why I keep saying that the start of the optical theme is the reason the memory theme is running. My belief is that only by following this technology and market shift can you hold real conviction and a real thesis in semiconductor, memory and optical investing from here.

Sources and verification

1. TrendForce, reporting on Rubin Ultra HBM configuration review, Aug. 4, 2026. Confirms evaluation of multiple configurations including 8-Hi HBM4E, 12-Hi HBM4 and 8-Hi HBM4 alongside 12-Hi HBM4E, and that the final spec is unset.

2. The Information, reporting on lower-capacity Rubin Ultra prototypes, 2026. Confirms prototype testing of 192GB and 256GB configurations.

3. SemiAnalysis, Vera Rubin analysis, 2026. Confirms the main configuration moving to HBM4 8-Hi 192GB with compute held and memory bandwidth slightly higher, and the view on the rack-to-rack optical link.

4. Damnang Research, What Does Rubin Ultra’s 8-Hi HBM Mean?, Aug. 10, 2026. Basis for the Section 1 field checks, the NVL576 and NPO structure, the software hierarchy and the HBM revenue sensitivity.

5. Kim, B. et al., Co-packaged optics for high-performance computing and artificial intelligence, Nature Electronics (2026). Basis for electrical interconnect limits, the CPO integration hierarchy, and the photonic interposer and XPU/memory pool architecture.

6. NVIDIA, “NVIDIA Vera Rubin POD: Seven Chips, Five Rack-Scale Systems, One AI Supercomputer,” 2026. Confirms the 8-rack, 576-GPU NVLink domain and the direct optical rack-to-rack connection in NVL576.

7. Marvell, “Scale-up Network Solutions for AI Infrastructure,” 2026. Confirms NPO and CPO product positioning and packaging differences.

8. Marvell, “The Evolution of AI Interconnects.” Describes the architecture in which the optical engine moves closer to the XPU from NPO to CPO.

9. NVIDIA, “NVIDIA AI Ecosystem Expands as Marvell Joins Forces Through NVLink Fusion,” Mar. 31, 2026. Confirms Marvell’s NVLink Fusion compatible scale-up networking, the silicon photonics collaboration and NVIDIA’s $2B investment.

10. Marvell / SK hynix, “Accelerating AI Infrastructure with Marvell Structera A and SK hynix CXL Memory,” Aug. 5, 2026. Confirms CMM-Ax co-development and the CXL-PNM structure.

11. Marvell, “Marvell Advances AI Memory Infrastructure Portfolio to Accelerate Agentic AI Inference,” Aug. 4, 2026. Confirms the 32TB, 50m and 2 to 3x token throughput vendor targets for the Photonic Fabric shared-memory tier.

12. Marvell, “Marvell Completes Acquisition of Celestial AI,” Feb. 2, 2026. Confirms completion of the Photonic Fabric acquisition.

HBF's name leads many investors into technical misunderstanding. The technology itself also remains contested, on access latency, endurance under repeated writes, heat and packaging yield.

Earlier this year I reviewed the H3 paper published by SK hynix on what HBF means technically and where its limits are.

This article analyzes the HBF that Sandisk presented at its Investor Day and in related public materials, and estimates bottom up how much the technology could move Sandisk’s share price if it reaches commercial deployment.

The report judges HBF’s commercialization prospects in four steps.

Section 1 compares the four architectures Sandisk presented in terms of data placement, write load and latency, and identifies which configuration is technically most realistic. It focuses on what the presentation did not sufficiently explain, namely KV cache write burden, prefetch, heat and endurance, and examines the conditions under which each architecture holds.

Section 2 examines HBF’s competing technologies, asks why HBF is needed relative to them, and tests whether it can lower system TCO despite its complex packaging cost.

Section 3 compares the platform structures of Google, Meta, Tenstorrent and NVIDIA, and analyzes technically why Google and Meta have a relatively strong incentive to evaluate HBF while NVIDIA is judged unlikely to.

Finally, Section 4 uses accelerator unit pools, HBF attach rates and stacks per accelerator at Google and Meta to derive Sandisk’s direct HBF revenue bottom up, and separates the second-order effects on product mix, NAND wafer absorption and revenue structure that could matter more to the share price.

For investors who have wondered how HBF actually works and what it could mean for Sandisk’s revenue and share price, this article is written for you.

Subscribe now

Disclaimer

This document is prepared for information purposes using public information and the author’s own analysis, and does not constitute a recommendation to buy or sell any security. Product specifications, participating companies and public roadmaps rely on disclosures from the companies and standards bodies involved. Items that have not been disclosed, including HBF and HBM data placement, cost structure and customer-level adoption likelihood, are identified as analytical assumptions or inference. Specifications, commercialization timing and customer adoption may change, and responsibility for investment decisions and their outcomes rests with the investor.

CONTENTS

1. Technical feasibility: comparing the four configurations

2. Economics: alternatives and capacity per package

3. Customer adoption

4. HBF’s economic impact: a Google and Meta bottom-up model

1. Technical feasibility: comparing the four configurations

The four configurations differ in what data HBF handles and whether HBM remains. HBF Only fills every stack site with HBF and stores both weights and KV cache there. HBF (+HBM) replaces only part of the stacks, splitting the roles with HBM.

HBM/HBF Cached places HBM as a front-end cache and stores weights and KV cache in HBF. Disaggregated separates prefill from decode and puts HBF on the decode accelerator to hold decode weights and KV cache.

The technical assessment that follows uses these data placement differences as its basis.

The first question is what role HBF can play in real inference workloads.

The four configurations differ in the data HBF handles and whether HBM remains. The comparison therefore uses write load, access pattern and latency sensitivity on a common basis rather than capacity alone.

1.1 HBF Only

HBF Only fills every stack site with HBF and uses no HBM. Because both model weights and KV cache reside in HBF, the configuration gains capacity but must also absorb the continuous write load of the KV cache directly.

In internal testing presented at Investor Day, four HBF-only accelerators matched the token-per-second throughput of eight HBM-only accelerators.

By the company’s explanation, the performance gap arises when HBM runs short of KV cache capacity, pushing some data into system memory and lowering GPU utilization. HBF relieves that capacity constraint by providing larger on-package capacity.

The company cited this as 8x capital efficiency and 2x GPU efficiency. The comparison is internal, however, and key premises such as GPU capacity and numeric precision may differ from real deployments.

The case for HBF Only therefore has to be verified in two steps.

First, whether the same on-package capacity shortfall still occurs on the latest accelerators and at lower inference precision.

Second, whether HBF can absorb the KV cache write load along with its thermal and endurance requirements.

The first issue is the comparison conditions.

The presentation used 192GB of HBM per GPU and BF16 to derive 960GB of weights for a 480B model, and concluded that eight accelerators were required once KV cache was included. Applying FP8 reduces the same weights to 480GB, and in the 288GB-per-GPU environment this report uses as its basis, the weights themselves fit within the combined HBM capacity of two accelerators.

The HBM left after loading weights can serve KV cache and runtime, though the actual headroom depends on KV cache, activation and runtime configuration. The capacity shortfall the presentation assumes may therefore be weaker than stated, but that does not mean two accelerators are sufficient for the entire serving footprint.

The second issue is the write behavior of the KV cache.

In HBF Only, KV cache is written directly to HBF. New data is written on every token and discarded when the session ends, so unlike read-dominant model weights it produces a continuous write load. NAND flash carries cell endurance limits under repeated writes. Any structure that writes KV cache directly to HBF must therefore treat write lifetime and thermal management as design variables.

Published on August 12, 2026, Li et al. (2026, arXiv:2608.11668) evaluated HBF-based KV serving using four production traces and five dense and MoE models. Write traffic exceeded read traffic across every trace, thermal limits were reached before peak bandwidth, and TLC configurations wore out faster than the SSD pool being replaced. The conclusion is that without SSD-class write management, storing transient KV cache directly in HBF is not sustainable. HBF Only has no HBM cache or write buffer, so it is the most exposed to that constraint.

Follow-up studies released on August 14 assess HBF in more conditional terms.

Son et al. (2026, arXiv:2608.13868) finds that HBF can raise batch size and throughput and reduce GPU count, but only on the premise of read bandwidth close to HBM and substantial endurance improvement.

Kim et al. (2026, arXiv:2608.14333) reports 1.94x throughput from a structure that separates immutable weights from mutable KV cache and supplies them over two parallel paths. Both are simulations, and both point to data type and movement path separation mattering more than capacity.

Taken together, I judge HBF Only to have low applicability to general conversational inference.

The more plausible fit is batch-style workloads that generate limited KV cache while repeatedly reading large weights or reference data. Where session counts and context lengths keep growing, KV write load rises and the applicable range narrows without additional write-management technology.

1.2 HBF (+HBM)

HBF (+HBM) configures k of N stack sites as HBF and keeps the rest as HBM. The essential feature is that data placement between HBF and HBM can be split according to workload characteristics.

This article takes as its base case a configuration that places model weights in HBF and KV cache in HBM. That separates the continuous KV cache write load, the largest constraint in HBF Only, from HBF.

The company has not disclosed the value of k, the data placement criteria between HBF and HBM, or the software policy. The assessment below therefore rests on the analytical assumption that weights sit in HBF and KV cache remains in HBM.

That assumption aligns reasonably well with HBF’s physical characteristics and the access profile of model weights.

First, model weights are written at load time and thereafter mostly read during inference, so the endurance burden from repeated writes is limited.

Second, weight access is dominated by large sequential reads at layer granularity, which matches NAND’s page-level read behavior comparatively well. It wastes less of each page read than small random access would.

Third, where the next required weight location is predictable, prefetch can overlap flash’s microsecond-class read latency with computation. Actual performance depends on prefetch accuracy and software scheduling.

The study cited above likewise assessed read-dominant model weights as a comparatively good fit for HBF, provided that placement is selective and that write budgeting and thermal control are in place.

Under this report’s assumptions, at k=4 node memory capacity rises from 288GB to 2.2TB while total bandwidth falls from 22TB/s to 17.4TB/s. As k increases, HBF capacity expands but HBM capacity and bandwidth decline.

The optimal k therefore depends jointly on weight size, KV cache demand and the bandwidth loss that can be tolerated.

HBF (+HBM) applies best under two conditions.

First, model weights must be large enough, in the hundreds of GB or more, that HBM alone cannot hold them. Second, data placement and prefetch must be optimizable alongside the accelerator software. The remaining item to verify is whether throughput and latency hold at target levels once prefetch is applied.

1.3 HBM/HBF Cached

HBM/HBF Cached uses HBM as a low-latency cache tier and stores both model weights and KV cache in HBF. It reduces the frequency of HBF access relative to HBF Only, but the write constraint persists as long as KV data lands in HBF.

This configuration favors services where identical or similar contexts are referenced repeatedly and a high cache hit rate can be sustained. Document-grounded question answering and workloads that repeatedly reference the same codebase are plausible candidates. In general conversational services where context differs sharply by session, HBF access and write load rise and applicability falls.

1.4 Disaggregated

The Disaggregated configuration separates prefill and decode accelerators. In the published diagram, GDDR is used on the prefill side while decode-side HBF stores decode weights and KV cache.

The assessment differs by data type. Decode weights are read-dominant after the initial load and fit HBF well. KV cache still requires write management, since new K and V are written on every token even during decode.

Separate from technical feasibility, the economics against competing architectures also need checking. The comparison cases in this report already include disaggregated designs that use no HBF, such as a GDDR7-based prefill accelerator and an SRAM rack for decode. For an HBF-based disaggregated design to be adopted, it must demonstrate an advantage in cost per token or system efficiency over those designs.

1.5 Assessment across the four configurations

The relative appeal of the four configurations comes down to what data sits in HBF and how much writing that data generates. Placing read-dominant model weights in HBF carries a light endurance burden, while writing KV cache directly to HBF adds write management and thermal control on top.

The following sections provide an in depth analysis of the HBF architecture.

The analysis examines alternative technologies that could compete with HBF, the technical factors that could nevertheless support HBF adoption, the types of customers most likely to deploy it, and whether NVIDIA could become one of them.

Finally, a proprietary analytical model is used to assess how HBF commercialization could affect Sandisk’s share price.

Read more

Earlier this year, the theme that led the market’s big rally was without question the optical sector. Almost every optical stock set new all time highs, from at least 100% to several hundred percent, and every investor was looking at optics.

But was it that they had run up too far?

From June on, the entire market including semiconductors and memory began to correct, AI skepticism started to surface, and the optical sector too had to watch its share prices fall by more than half from the highs.

Some investors caught in the drawdown left the game altogether, saying the optical sector was finished.

And now in August, share prices look to be riding an upward trend again on the back of earnings from several optical companies.

Is this really the time to come back to optical investing?

Or is it only a temporary bounce, with a sharp rise like the one earlier this year unlikely for a while?

In fact, there was a slight correction after AEHR’s earnings release, but up to now optical stocks have been in an uptrend.

In this article, I want to lay out, in detail, the round two optical investing strategy that follows my earlier optical investment map.

Why this correction happened, where optics stands now and what points to look at closely, and if you were to start investing in the optical sector fresh at this point, which layer and which names in this complex optical ecosystem you should look at first.

If you are an investor who is going to take another serious look at the optical sector, I hope you read this article through.

Disclaimer

This article is personal analysis and is not investment advice. All investing should be done based on your own research. The author may hold positions in some of the names discussed and may change those positions without prior notice.

Why the June and July Correction Happened

The starting point of the optical correction was SemiAnalysis’s CPO analysis. Along with the provocative phrase Massive Delay, it argued on the basis of low yields and cost burden that CPO mass production in the scale up segment would be pushed out from late 2028 to beyond 2029, and that until then copper and pluggable modules would keep the upper hand. After that publication, valuation adjustment appeared across the optical communications value chain.

On top of this, as AEC (Active Electrical Cable, a copper cable with a signal restoration chip built in) shipments grew quickly, a market consensus formed that in rack connectivity would be handled by copper for the time being, and the Optical I/O argument, that the transceiver module market shrinks once the electrical to optical conversion moves inside the GPU package, came back into focus as well.

Beyond that, optical stocks were already at three digit price to earnings ratios, so profit taking and index rebalancing compounded and the drawdown widened.

Subscribe now

August, What Changed

On August 11, Lumentum said demand for ultra high power CPO lasers is increasing, that it had received an initial order for ELS modules, and that several NPO engagements are underway.

For its lead CPO customer, it said high volume shipments for scale up begin in the second half of 2027 with customer deployment in 2028.

The next day Coherent said there had been no case at all of CPO demand being pushed out and that customer interest had in fact increased.

It added that scale out CPO revenue, connecting rack to rack, begins in the second half of 2026, that scale up, which ties multiple compute racks together within a cluster, follows in 2027, and that it is engaged with multiple customers on both CPO and NPO.

SemiAnalysis’s claim that NVIDIA’s scale up CPO mass production could be delayed beyond 2029 was confirmed to be untrue through the earnings calls of these two companies.

On top of this came OCS (Optical Circuit Switch) results.

OCS is equipment that switches the optical path directly instead of using an electrical switch, reducing the number of electrical switching hops. As Google shifted from what it had developed in house to external sourcing, Lumentum announced it had secured a backlog of more than $400 million from three new customers and will ship roughly $400 million in the second half of 2026. Coherent has already announced initial revenue, and on August 12 raised the size of this market to more than $4 billion.

Another of the most important items was Aehr’s earnings.

Test equipment orders are normally a leading indicator that runs several quarters to more than a year ahead of a customer’s production ramp, and Aehr guided FY2027 revenue to $130 million to $150 million, 2.6x to 3x the prior year, of which $100.6 million was announced as effective backlog already received. Its lead silicon photonics customer is already running an unmanned automated line, a follow on production order came in early August, and a new customer has already placed an order for four systems within a few months of first contact and taken delivery, so the order data showed that optical production ahead is going to grow much larger.

Subscribe now

Why Optics, Why Now, Again

As we saw above, the fundamentals of optics have not changed. If anything, guidance has moved higher through this August earnings round. Coherent’s FY2027 first quarter guidance has a low end above the quarter just reported and gross margin is heading up as well. What fell in June and July was not earnings but the valuation multiple.

That optical connectivity grows as AI data centers get bigger is something no investor with conviction in this sector disagrees with. The problem was the market’s misunderstanding that this optical demand was tied to a single CPO timeline. Exactly as I emphasized in my earlier scale up CPO article, Coherent in this earnings round also reconfirmed that the content opportunity it captures is similar whether things go the CPO way or the NPO way.

Supply is still a bottleneck as well.

InP (Indium Phosphide, the compound substrate that laser chips are made on) wafer capacity is expected to grow by 20 to 30 times through 2029, and until then it looks unlikely to keep up with demand. Lumentum’s revenue and operating margin rising together in the quarter just reported is read as a positive signal that this supply bottleneck is currently converting into profitability.

More important is that optical investors’ sentiment is coming back. On August 4 there was a report that the FCC is preparing a draft rule restricting imports of new Chinese optical transceivers, and after that report the share prices of several optical stocks rose sharply.

Whether this regulation actually gets finalized remains to be seen, but it was good signal news in the sense that investors were reminded once again of how geopolitically important the optical theme is in its connection to AI. In addition, LYTE, the ETF that holds only the optical value chain, traded $72 million on its first day of listing on August 6. That is a bullish factor for optical investing and at the same time a crowding signal.

Subscribe now

Still, what makes optical investing hard is that the optical ecosystem itself is so complex, and that each of these factors does not apply to every layer at the same time. To resolve this complexity, back in April I wrote an optical investment map. In this article I intend to use the layer map from that map again for analysis.

Unlike last time’s broad overview, in this article I plan to approach it from a perspective that is more useful to investors. In the end what investors are most curious about is, if I had to start optical investing now, again, which layer and which names among this many layers and names I should look at first, and how to think about investment strategy.

In the rest of this article I want to analyze this investment perspective in detail, together with the current state of optical technology development analyzed above.

Subscribe now

If You Were Starting Optical Investing Now

A note on reading the table

The names highlighted in yellow are ones the author has classified as priority watch candidates according to his own criteria, based on results disclosed to date and the outlook ahead. Whether a name is highlighted is not a recommendation to buy or sell, and a name that is not highlighted does not mean it is unsuitable for investment. The selection criteria and judgments are entirely the author’s own, and investment decisions should be made through your own research.

Read more

Since SemiAnalysis published its institutional report on the HBM4 8-Hi despec, a wide range of interpretations and speculation surrounding it has spread quickly through the market.

As someone who covered the HBM4 8-Hi story in an article about a week ahead of SemiAnalysis, I will also admit that every time I saw misunderstandings and conjecture get amplified and reproduced from fragmentary numbers and information, without a sufficient understanding of the technical context of the matter, it genuinely saddened me.

This article was written conclusion first, and that part will be open to both free and paid subscribers. There is a lot of market misunderstanding around this HBM4 8-Hi move, and I judged that making my analytical view on it public would be meaningful in its own right.

In the paid section that follows, I will walk through, in order, why HBM4 8-Hi emerged, how it became possible, whether memory makers’ revenue will actually head lower, and what to watch going forward for each memory maker. I am confident that this article will be the deepest analysis yet of the technical background and meaning of HBM4 8-Hi, which the market has not properly covered so far.

I hope this piece clears up at least some of the market’s unnecessary misunderstandings around HBM4 8-Hi, and helps investors view this change on a more accurate technical footing.

Disclaimer

This article is written for informational purposes and does not recommend buying or selling any particular stock. Responsibility for investment decisions and their outcomes rests with the investor. The Rubin Ultra specifications in this article are reported configurations under review, not confirmed facts, and the final specifications may change. The figures are based on public reporting, standard specifications, and my own calculations and illustrative assumptions. Anything attributed to industry chatter is hearsay that has not been publicly confirmed.

Subscribe now

Conclusion

To sum up this article, I do not see this 8-Hi transition as a bad signal for memory. This is a market where HBM cannot be sold for lack of it, and I see the HBM4 8-Hi despec as a special measure by NVIDIA to build more GPUs out of that scarce HBM. As discussed in the body, this despec is a move that would be hard for anyone but NVIDIA, which has built technical vertical integration spanning chip design, optics, and software.

Also, despite this despec, my calculations suggest the ratio of output gains to HBM price decline can come out higher, so total HBM revenue holds at 81.5% to 98% of planned 4E revenue. This means that if 12-Hi HBM4E could not actually meet more than 81.5% of the required volume, this despec can actually result in higher revenue.

Of course, what this NVIDIA request means for the memory makers is also significant. As I said in a previous article, NVIDIA has shown through this despec card that it has the influence to actually steer memory price negotiations.

Conversely, I think this may be a case that illustrates the view of SK hynix Chairman Choi Tae-won, that current memory prices are too high and that suppliers should move forward together with customers by coordinating them well.

In the end, I think it would be hasty to read this despec as a signal that the memory cycle has broken, and the right way to read it is as a signal that suppliers and customers have entered a phase of moving together, coordinating price, volume, and even design approaches.

Table of Contents

1. Why 8-Hi HBM4 Instead of 12-Hi HBM4E

2. Is the Performance Possible with 8-Hi 192GB

3. Does Memory Supplier Revenue Shrink

4. What It Means for Each Memory Supplier and the Optical Names

Further reading

Read more