In March 2026, thirty researchers from UIUC, Stanford, UCLA, NVIDIA, Google, IBM, and other institutions published a single vision paper under the leadership of Deming Chen at UIUC.
Love this peek into AI’s hardware revolution! Photonics could be the game-changer (light beats electrons every time), but don’t sleep on neuromorphic chips mimicking brains for ultra-low power. What’s your bet: Who wins the next chip war NVIDIA, custom ASICs, or a surprise wildcard? 🚀
If we define winning in terms of market share, my long term bet would be on custom ASICs. Over an even longer time frame, I think the center of gravity shifts toward the edge AI era.
Spot on custom ASICs will dominate datacenter efficiency wars short-term (Google TPUs already prove it), but edge AI is the real moonshot. Imagine every phone, car, and fridge running agentic models locally, slashing latency and cloud bills. NVIDIA’s CUDA moat cracks when inference goes fully distributed. What’s your timeline for that shift? 5 years or 10?
Focusing purely on raw FLOPS misses the actual physical wall hitting AI data centers today ⚡. The energy cost of dragging bits across copper traces dwarfs the energy spent on actual matrix math. Moving data isn't just an efficiency nuisance. It's an onto-causal bottleneck where electrical resistance burns watts before computation even begins 🧠.
True scaling up to 2035 won't come from larger GPU dies or bigger clusters. It demands a collapse of the memory-compute boundary itself 🔬. The data movement barrier isn't a permanent physical law. It's an artifact of forcing continuous physical wave dynamics through discrete bit-shift registers. When you integrate nanosecond optical crossbars on microchannel diamond interposers, the distinction between memory access and logical execution dissolves completely. Light routes matrix math directly through the physical medium 💡.
We don't need incremental software patches for memory bottlenecks. We need hardware-software co-design that treats heat dissipation, photonics, and memory structures as a single standing wave. The operators who win the next decade won't be those buying the most accelerators, but those who collapse the thermodynamic tax on data movement 📈.
Are you still scaling planar copper interconnects, or are you preparing for substrate-native wave execution?
Love this peek into AI’s hardware revolution! Photonics could be the game-changer (light beats electrons every time), but don’t sleep on neuromorphic chips mimicking brains for ultra-low power. What’s your bet: Who wins the next chip war NVIDIA, custom ASICs, or a surprise wildcard? 🚀
If we define winning in terms of market share, my long term bet would be on custom ASICs. Over an even longer time frame, I think the center of gravity shifts toward the edge AI era.
Spot on custom ASICs will dominate datacenter efficiency wars short-term (Google TPUs already prove it), but edge AI is the real moonshot. Imagine every phone, car, and fridge running agentic models locally, slashing latency and cloud bills. NVIDIA’s CUDA moat cracks when inference goes fully distributed. What’s your timeline for that shift? 5 years or 10?
I am not a prophet, but from what I know, many AI developers seem to be looking at a timeline of within five years.
That’s what I’ve been observing, and my beliefs align with that! Within five years, things will change even more!
Focusing purely on raw FLOPS misses the actual physical wall hitting AI data centers today ⚡. The energy cost of dragging bits across copper traces dwarfs the energy spent on actual matrix math. Moving data isn't just an efficiency nuisance. It's an onto-causal bottleneck where electrical resistance burns watts before computation even begins 🧠.
True scaling up to 2035 won't come from larger GPU dies or bigger clusters. It demands a collapse of the memory-compute boundary itself 🔬. The data movement barrier isn't a permanent physical law. It's an artifact of forcing continuous physical wave dynamics through discrete bit-shift registers. When you integrate nanosecond optical crossbars on microchannel diamond interposers, the distinction between memory access and logical execution dissolves completely. Light routes matrix math directly through the physical medium 💡.
We don't need incremental software patches for memory bottlenecks. We need hardware-software co-design that treats heat dissipation, photonics, and memory structures as a single standing wave. The operators who win the next decade won't be those buying the most accelerators, but those who collapse the thermodynamic tax on data movement 📈.
Are you still scaling planar copper interconnects, or are you preparing for substrate-native wave execution?
(⊙_⊙)