Hyperscalers, meaning companies like Amazon, Microsoft, Google, and Meta that build massive data centers, spent about 8% of their total capex on memory in 2023 and 2024.
According to estimates from SemiAnalysis, that number climbs to around 30% in 2026. Nearly a fourfold jump in two years. AI has been vacuuming up memory, supply started falling behind, prices spiked, and even at those prices buyers still cannot secure the volume they need.
One of the cards hyperscalers have pulled out in this crisis is
CXL (Compute Express Link).
Just two or three years ago the industry pronounced it “dead in the AI era,” and several companies quietly shelved their CXL projects.
In 2026, the technology’s standing looks completely different.
Meta went as far as publishing a paper showing how it pulled aging memory out of servers headed for the scrap heap, revived it with CXL, and deployed it at scale in production data centers.
This article takes up three questions.
What is this technology, exactly.
Will it actually see broad adoption.
And if it does, which companies benefit and which get squeezed, and in particular, does HBM demand take a hit.
The last question gets answered with a single investment map: the CXL ecosystem broken into layers, controllers, modules, IP, switches, software, and optical interconnect, showing who occupies each layer, at which stage each layer starts making money, and how much of the expectation is already in the stock price.
Disclaimer
This article is for informational purposes only and does not constitute a recommendation to buy or sell any security. All judgments about the companies and technologies mentioned are personal opinions based on publicly available information, and responsibility for any investment rests with the investor.
Part 1. The Concept: What Is CXL
1. From the Ground Up: How Data Moves Inside a Computer
To understand CXL, you only need to grasp two concepts first: what PCIe is, and what a memory channel is.
Think of a computer as a city.
The CPU is city hall.
Every decision about who does what and when gets coordinated there.
The GPU is a giant factory.
City hall issues the orders, but the actual heavy labor, the AI computation, happens at the factory.
The SSD and the other components are buildings scattered across the city, and the city runs on data moving between these buildings and city hall.
PCIe (Peripheral Component Interconnect Express) is the city’s standard highway.
When you plug a graphics card into a motherboard, when you connect an SSD, it all rides this road.
Each generation gets faster: PCIe 6.0 is twice as fast as 5.0, and 7.0 doubles it again.
The speedups come from two levers.
Send trucks more often (push more electrical signals per second), or load more cargo onto each truck (pack more data into each signal). In practice, 6.0 doubled the information carried per signal (PAM4), and 7.0 doubled the signaling rate itself. There is also a lane count: x4, x8, x16, with more lanes carrying more data at once.
The names look complicated, but PCIe is simply the standard road that computer components use to exchange data.
Memory, meaning DRAM, has never used this highway.
Memory exchanges data with the CPU so frequently and so fast that the system puts a dedicated warehouse right next to city hall and lays a private direct road between them. That direct road is the memory channel. No traffic lights, city hall vehicles only, and incomparably faster than the highway.
The problem is that the number of these direct roads is fixed when the city hall building, the CPU, is designed.
The reason they cannot be added later comes down to the physical structure of the chip. Attaching one channel requires hundreds of pins (the metal contact points where wires connect) coming out of the CPU die, plus a memory controller circuit etched into the silicon to run that channel.
Pins and circuits are like doorways set in a building’s concrete: the moment the chip comes off the line, they are final. You cannot pave new direct roads to a finished city hall, so a server CPU with eight memory channels has eight, and one with twelve has twelve. You can build a bigger warehouse at the end of each road, but high-capacity modules get expensive fast. The total memory a server can hold is chained to the CPU bottleneck.
That constraint has been the founding assumption of server design for decades.
The factory (GPU) side solved the same problem in a more extreme way: it eliminated the need for roads entirely by stacking the warehouse directly on top of the workbench.
That is HBM (High Bandwidth Memory).
DRAM dies are stacked vertically inside the same package as the GPU and wired straight in through thousands of connections, so no road on earth can match it for speed.
The price is equally extreme. The moment the package is assembled, the capacity is locked forever, and the manufacturing difficulty makes it the most expensive memory there is. City hall and the factory end up trapped in the same dilemma: the faster the memory, the less freedom you have on capacity.
Will the Memory Stock Rally Keep Going?
SK hynix posted 72% operating margin in a single quarter. Micron is locking in 3-to-5-year supply agreements. Samsung had a quarter where conventional DRAM profitability exceeded HBM.
2. What Exactly Is CXL
CXL in one sentence: a standard that lets you put memory on the PCIe highway.
If you cannot pave any more private direct roads, the idea is to connect a distribution center to the highway that is already there. Getting to the distribution center means taking the highway, so round trips take a bit longer than the direct road. In exchange, you can build as many distribution centers as you want, at whatever size you want. Decoupling memory capacity from the CPU’s fixed count of private roads, and paying for it with a little speed, is the essence of the CXL trade.
But wait, does mixing in slower memory slow the whole system down?
It does not, because not all data demands top speed. Data has temperature. There is hot data you touch every moment, lukewarm data you look at a few times a day, and cold data you merely keep. Hot data belongs in fast memory, but there is no reason to give lukewarm data the most expensive seat in the house.
So a well-built system divides storage into tiers and places data in the tier that matches its temperature. This is memory tiering.
The real hierarchy is far more granular, from SRAM caches inside the CPU die down to archival storage, but for this story only two tiers matter.
In city logistics terms: the dedicated warehouse next to city hall, and the long-term storage warehouse on the outskirts. Closer means faster, pricier rent, and less space; farther means slower, cheaper, and vast.
In computer terms, local DRAM next to the CPU is the dedicated warehouse, and the SSD is the long-term warehouse on the edge of town.
This two-tier structure was good enough for decades. Most data was either hot or cold, and what little fell in between was small enough in absolute terms that buying a bit more DRAM covered it without strain.
However, AI changed the game.
First, the top of the pyramid ran out of speed. DRAM could not keep up with the pace at which GPUs churned out computation, so, as we saw in Section 1, a new tier appeared at the very top: HBM, the warehouse stacked directly on the workbench.
Then, even with a taller peak, capacity ran out. The data that needed processing swelled beyond what a single server’s DRAM could hold, and with DRAM prices soaring, the cost of “just buy more” became unbearable. For the first time, lukewarm data, too precious for the SSD but too wasteful for DRAM, started demanding a seat of its own. The dedicated warehouse (DRAM) and the outskirts warehouse (SSD) differ in round-trip time by a factor of several hundred, so a new tier was needed between them, and CXL memory slots into exactly that spot, the distribution center.
AI put HBM on top of the pyramid, and now it is wedging CXL into the middle.
The thing to remember is that CXL memory is not a picture of one memory displacing another. It is a picture of adding a floor to the pyramid. Getting this exactly right is very helpful for understanding the investment insights that come later.
With its place in the pyramid settled, what remains is how it works.
Technically, CXL keeps PCIe’s physical wiring as is and layers memory-specific conversation rules on top.
There are three: CXL.io for basic communication, CXL.cache for when a device peeks into the CPU’s cache, and CXL.mem for when the CPU reads and writes external memory as if it were its own. Devices are classified as Type 1, 2, or 3 depending on which rules they combine, and you can skip the taxonomy.
Just remember that in practice, “CXL memory” effectively means Type 3, a device that purely adds memory capacity.
Plug a Type 3 device into a server and what does the operating system see?
A chunk of memory with no CPU attached. Essentially a warehouse that sits a little farther away, and operating systems already know how to handle this distinction between near and far memory (it is called NUMA, Non-Uniform Memory Access).
Linux already supports CXL memory in the mainline kernel, and Windows Server 2025 is bringing in CXL memory support in preview form. The software groundwork is effectively in its final stretch.
That covers how a single Type 3 device works. But the same Type 3 memory serves completely different purposes depending on where and how it is installed. Deployment evolves in three stages.
First, direct attach.
A CXL memory module in an SSD-like E3.S form factor plugs into the server. The name invites confusion, but there is no exotic new memory chip inside: the module holds ordinary DRAM, and the CXL controller chip next to it simply translates that DRAM into PCIe language and puts it on the highway. Latency is lowest and the structure is simplest, which is why this is where real volume is flowing today.
Second, pooling.
Dozens of memory modules sit behind a distribution box called a CXL switch, and multiple servers draw from them as needed. A shared distribution center serving several city halls. This matters because data centers have a serious “bought memory sitting idle” problem. Every server gets fully stocked with memory sized for peak demand, and most of the time a good chunk of it sits empty. It is like building a warehouse for the busy season and leaving it half empty most of the year, and this locked-up idle memory is called stranded memory. With a shared distribution center, each city hall keeps only the warehouse it normally needs and rents space from the center when volume surges. Commercial memory pools in the 100TiB class already exist.
Third, fabric.
Possible from CXL 3.1 onward, this is the stage where an entire rack, or several racks, shares one giant memory pool. The goal extends to multiple servers reading the same data together without copying it. Technically the most ambitious stage, and, as we will cover later, the least proven one.
That leaves one last question: how much speed do you actually give up using CXL memory?
The conventional wisdom says “it is far away, so it is too slow to use.” Measurements say otherwise.
In a public demo by controller maker Montage Technology, a server with 1TB of plain DRAM was compared against a server mixing 512GB of DRAM with 512GB of CXL memory, running a database workload. Application-level latency rose by 5 to 10µs (microseconds), while throughput came in at 95 to 100% of the DRAM-only baseline.
With a design that keeps lukewarm data in the distribution center, the perceived penalty has shrunk to nearly nothing.
Part 2. The Verdict: Will It Actually Get Used, and Who Wins
3. So Why Was It Declared Dead
The CXL standard launched in 2019 under Intel’s leadership, but the memory industry pushed it hardest. Samsung opened the game in 2021 with the industry’s first CXL memory expansion device, and even as DRAM slid into a historic glut and price collapse in 2022 and 2023, memory makers kept expanding their CXL lineups.
The math was that lifting the channel constraint would raise the total DRAM per server and create a new outlet for surplus inventory. For memory companies, CXL was a technical standard and, at the same time, a sales pitch for moving more DRAM through a downcycle.
Then the AI boom hit in 2023, data center budgets stampeded toward GPU clusters, and nobody was left to listen to the memory industry’s pitch about loading servers with more DRAM.
AI at the time meant large-scale training, and training means lashing thousands of GPUs into one block that exchanges data nonstop, a world where bandwidth, the road’s total carrying capacity, is everything.
The buyers’ question changed from “how much memory can I put in a server, how cheaply” to “how fast can I link GPUs to each other.”
And that world had its own roads. Unlike PCIe, the standard road linking components inside one computer that we saw in Section 1, GPU-to-GPU links get dedicated roads like NVLink, and server-to-server links get a separate road called Ethernet.
Why these roads beat PCIe comes down to paving technology. The wiring technology that fires data between chips is called SerDes (Serializer/Deserializer), and you can think of it as the pavement that determines how much speed a single lane can handle. At the time, PCIe-class SerDes offered low error rates and low latency but comparatively low speed, while the class used by NVLink and Ethernet (112G, 224G) gave up a little on errors and latency and ran roughly three times faster.
In a training world where bandwidth was everything, that 3x gap was fatal. For a chip designer, spending precious die area and power on PCIe/CXL meant forfeiting the chance to run wiring three times faster with the same resources.
So between 2023 and early 2024, hyperscalers and major semiconductor companies suspended or killed CXL projects one after another.
In early 2024, the semiconductor research outlet SemiAnalysis published an analysis titled “CXL Is Dead In The AI Era,” and its diagnosis, a market where only the sellers were enthusiastic and the buyers had left, became the industry consensus.
That diagnosis was not wrong for its time.
But it rested on one assumption: that AI workloads meant training.
What changed was not so much the CXL technology as that assumption.
4. Three Reasons This Time Is Different
The first change: the workload shifted from training to inference.
Inference is what happens when an AI service like ChatGPT actually answers a user’s question. Inference has a different bottleneck than training. When an AI works through a long conversation or document, it stores intermediate results in memory so it does not have to recompute everything it already read. That notepad is the KV cache. It snowballs as the conversation grows, and on the latest large models the KV cache alone eats 80 to 120GB per GPU. HBM is a resource where adding capacity is brutally expensive, so keeping this entire notepad in HBM is like stacking newspapers in a bank vault.
The approach of pushing rarely-read notes down to CXL memory came out of exactly this, and public demos are reporting meaningful gains in throughput and energy per token. In the age of inference, capacity matters as much as bandwidth, and capacity is what CXL does well.
The second change: the economics of the memory crisis.
Look at the numbers from the opening again. Memory going from 8% to 30% of hyperscaler spending. When DRAM gets this expensive and this hard to find, two behaviors become rational. One is not letting the memory you already bought sit idle: pooling. The other is reusing memory you were going to throw away.
The Vistara paper Meta presented at ISCA 2026 is exactly the latter. Meta pulled DDR4 memory from servers at end of life, attached it via CXL as expansion memory for new DDR5 servers, and deployed it at hyperscale in production. It built everything itself, from a dedicated ASIC to operating system support. A calculation that never penciled out when memory was cheap now pencils out because of the memory crisis.
The third change: the underlying PCIe got fast enough.
The 3x relative gap with the Ethernet class from Section 3 has not closed, since both sides keep evolving, so CXL still is not replacing the GPU expressways. But for memory expansion, its native job, what matters is the absolute bandwidth the PCIe link itself carries, and that bandwidth has crossed into memory-channel territory. A PCIe 5.0 x16 link at roughly 64GB/s per direction was worth just over one DDR5 memory channel (about 51GB/s per channel), but PCIe 6.0 x16 at roughly 128GB/s does the work of two and a half channels. With a single CXL link starting to deliver genuine memory-channel bandwidth, the road to the distribution center has finally gotten wide enough to make the distribution center worth using.
The proof that these three changes are not just theory is named commitments from the demand side. A technology pushed by vendors and a technology deployed by buyers carry different weight, and through 2023 CXL was the former. Not anymore. Microsoft unveiled CXL-attached memory in its Azure M-series VM preview in November 2025, and Meta published the full-stack paper described above.
The spec and the ecosystem followed.
CXL 3.1 became the default target for new server platforms, CXL 4.0 arrived in November 2025 with bandwidth doubled to 128GT/s on a PCIe 7.0 base, and a large share of new server platforms are now designed with CXL support as a given.
The question of whether servers support it is settled, the question now is how much gets used.
