Damnang Research

Damnang Research

The Next Memory Race Will Not Be Decided by Scaling Alone

An SK hynix process expert on 3D DRAM, separating cells and peripheral circuits, HBM, and AI systems

Damnang's avatar
Damnang
Oct 06, 2026
∙ Paid

Interview: September 19, 2026, Pacific time · Approximately 90 minutes
Interviewer and editor: Damnang
Expert: Process development engineer at SK hynix’s future technology research institute


Where the conversation began

Does a lead in HBM translate into a lead in the next generation of memory technology? This conversation made me reconsider that question.

The expert I spoke with develops next generation DRAM processes at SK hynix’s future technology research institute. We began with 3D DRAM, where the cell structure itself is built in multiple layers, then moved to fabricating cells and peripheral circuits separately and bonding them together, HBM manufacturing and customer support, and the role memory companies want to play in AI systems.

What stood out was that the basis of competition differed by technology. In 3D DRAM, fabricating structures laterally inside the stack was closely tied to identifying which internal layer had a problem. With cell and peripheral circuit separation, increasing cell density and improving peripheral circuit performance had to be considered separately.

The expert expressed confidence in the company’s collaborative culture and customer support, while also discussing the limitations of a strategy focused on scaling and the difficulties of new bonding technologies. This report includes not just those conclusions, but the reasoning and practical examples behind them.


Key takeaways

01 | 3D DRAM faces bottlenecks in both fabrication and validation. Alongside the difficulty of lateral etching and film formation, the speed of detecting internal defects constrains how quickly the next process conditions can be determined.

02 | Separating cells and peripheral circuits changes the basis of competition. Freeing up cell area and developing peripheral circuits independently creates performance and cost options beyond moving to a smaller node.

03 | Start by distinguishing what is being bonded. Bonding cell and peripheral circuit wafers and stacking individual dies for HBM begin from different foundations and face different mass production challenges.

04 | AI memory strategy depends on design, process, and collaboration capabilities. Proposing a memory tier, designing it, and connecting it to other processes or companies are tasks that have to be prepared together.

Editorial note

This is a thematic edit of the original interview, not a verbatim transcript. Questions and answers have been edited for clarity, and related remarks have been connected. The expert’s answers reflect personal views at the time of the interview and do not represent the company’s official position. Background beyond the transcript appears separately, with sources, under ‘Technical background, Editor’s supplement.’ ‘Damnang’s interpretation’ represents the editor’s assessment. Generative AI was used to assist with wording and editing.

Keep reading with a 7-day free trial

Subscribe to Damnang Research to keep reading this post and get 7 days of free access to the full post archives.

Already a paid subscriber? Sign in
© 2026 Damnang2 · Privacy ∙ Terms ∙ Collection notice
Start your SubstackGet the app
Substack is the home for great culture