Just a few years ago, the semiconductor industry’s biggest talking point was “which company will capture the leading-edge nanometer process first.” Every semiconductor company rushed to emphasize how many nanometers their products were. However, in 2026, intertwined with the AI era, the semiconductor industry’s paradigm is passing through a clear turning point.
The Limits of Process Scaling
Samsung and TSMC are approaching 2nm process mass production, and Intel has entered preparation for 18A (1.8nm-class) process manufacturing. But as processes become finer, semiconductors hit three fundamental limits.
First, cost increases overwhelm performance gains. From 7nm to 5nm, from 5nm to 3nm, wafer costs increase 30-40% per node while performance improves only 10-15%. Development costs and mask expenses for each process step increase exponentially, rapidly deteriorating economics.
Second, physical limits have become visible. As transistor gate lengths shrink to several nanometers, physical limits like quantum tunneling, leakage current, and process variation have materialized. Overcoming these requires new transistor structures like GAA (Gate-All-Around), which also drive costs skyward.
Third, AI workloads can’t be solved by process alone. AI chip bottlenecks aren’t computational speed but data movement. No matter how fast you make GPU cores, performance stagnates if memory bandwidth is insufficient. Process scaling can’t solve this problem.
Three Critical Advantages of Packaging
Packaging provides a practical solution to elevate system performance while circumventing process scaling limits.
First, heterogeneous integration is possible. Chips made with different processes can be combined in one package. AMD’s Instinct MI400 series unveiled at CES 2026 is representative. The MI455X integrates 12 compute dies and I/O dies made with TSMC 2nm and 3nm processes in one package. Producing each die at its optimal process node and integrating at the packaging stage maximizes cost efficiency—far more economical than implementing all functions on a single cutting-edge process.
Second, it fundamentally solves memory bandwidth problems. NVIDIA H200 provides HBM3E 141GB and 4.8TB/s memory bandwidth. AMD MI455X achieves 432GB memory capacity and 19.6TB/s bandwidth with 12 HBM4 stacks. This is possible because GPU dies and HBM are placed millimeters apart on a 2.5D interposer. The same performance would be physically impossible with GDDR memory on a PCB substrate. Shorter signal distances increase bandwidth and reduce power consumption.
Third, it secures both yield and flexibility. Large monolithic dies see yields drop exponentially as area increases. If a wafer has several defects, larger dies are more likely to encounter them. Dividing into multiple small dies keeps individual die yields high, and only defective dies need replacement. Intel’s Core Ultra Series 3 (Panther Lake) announced at CES 2026 separately manufactures CPU, GPU, and I/O tiles and stacks them with Foveros 3D packaging. If one tile has issues, only that tile needs replacement rather than discarding the entire unit.
The definition of a “good chip” has changed. High transistor density alone isn’t enough—actual performance is determined by how efficiently multiple dies are connected, power is supplied, and heat is removed. All of this falls under packaging technology.
In conclusion, as of 2026, semiconductor industry winners are determined not by “who has the finest process” but by “who has secured advanced packaging capacity.”
2. The Three Evolution Axes of Semiconductor Packaging
Packaging technologies can be divided into three axes.
Area expansion axis: Meeting demand for larger chips by creating bigger packages. Starting from 2.5D interposers (CoWoS, EMIB), evolving beyond wafer size limits to panel-level packaging (CoPoS).
Density maximization axis: Stacking chips vertically to increase connection density. Hybrid bonding (SoIC, Foveros Direct, X-Cube) is core, with HBM stacks also belonging here.
Bandwidth breakthrough axis: Increasing data transfer speeds between chips and packages. Represented by chiplet standards like UCIe and optical interconnects like CPO (Co-Packaged Optics).
These three axes aren’t independent. For example, chips can be stacked with hybrid bonding on a 2.5D interposer, communicate via UCIe, and send data outside the package via CPO. Actual AI systems are built combining these technologies.
2.1 Area Expansion Axis: 2.5D → Panel Level
AI chips keep getting larger. NVIDIA’s GB200 Superchip is a large package integrating two Blackwell GPUs and one Grace CPU. AMD’s MI455X also integrates 12 HBM4 dies and 12 compute/I/O dies made with 2nm/3nm processes in one package. The problem is that manufacturing such large packages on 12-inch (300mm) wafers is inefficient. Placing rectangular packages on round wafers wastes edge area, and wafer output per wafer drops sharply as packages grow.
CoWoS is currently the most widely used 2.5D interposer technology, but as large-area package demand continues growing, it hits wafer-based production limits. TSMC is developing CoPoS (Chip on Panel on Substrate) to address this. Using large square panels (310mm x 310mm) as substrates instead of wafers significantly improves area utilization and enables larger packages.
Industry reports indicate CoPoS will go through pilot lines in 2026 targeting mass production in 2028-2029. However, recent Nomura reports suggest CoPoS mass production might delay to 2029-2030. Transitioning to panel level requires changes across equipment, materials, and processes, taking time, but long-term it’s likely to become the mainstream production method for large AI packages. NVIDIA is expected to be the first major customer.
Samsung is also developing FOPLP (Fan-Out Panel Level Packaging), and Powertech has been mass-producing under the name PiFO since 2019. Fan-out originally makes redistribution layers wider than chips to increase I/O density—doing this at panel level simultaneously achieves large area and high density. However, most industry observers see TSMC CoPoS as more likely to capture the market first.
2.2 Density Maximization Axis: Hybrid Bonding & 3D Stacking
2.5D places chips side by side horizontally. 3D stacks them vertically. Vertical stacking can integrate more functions in the same area and drastically reduces chip-to-chip distance, simultaneously improving bandwidth and power efficiency.
Traditional 3D packaging used micro bumps—solder balls placed at tens of micrometers pitch to connect stacked chips. But entering the AI era, micro bump limitations became clear. Pitch is hard to reduce further, and low connection density limits bandwidth.
Hybrid bonding is a game changer. It simultaneously bonds copper (Cu) pads and silicon oxide (SiO₂), creating direct Cu-Cu connections without solder. Pitch can be reduced below 10 micrometers, and TSMC is already mass-producing with SoIC technology. Intel’s Foveros Direct has 9-micrometer pitch for gen-1, targeting 3-micrometer for gen-2. Samsung’s X-Cube is also hybrid bonding-based, with 2026 mass production timeline discussed.
As pitch shrinks, connection point counts increase exponentially. If you can make 10x more connections in the same area, data transfer bandwidth also increases 10x while power per signal line decreases. This is hybrid bonding’s core value.
However, hybrid bonding has very high technical difficulty. Cu surfaces must be nanometer-level flat, and even a single dust particle causes bonding failure. Stacking materials with different thermal expansion coefficients creates stress during temperature changes that can cause cracks. Achieving high yields requires extremely precise control of surface treatment, alignment, bonding pressure, and heat treatment conditions.
HBM is also a representative 3D stacking case. Current HBM3E mainstream is 8-12 stack layers, with HBM4 planned up to 16 layers. However, entire HBM stacks won’t immediately transition to hybrid bonding. A hybrid approach is realistic: DRAM-to-DRAM connections continue using micro bumps and TSVs, with hybrid bonding applied only between logic dies and the first DRAM layer. Converting everything to hybrid bonding first requires solving yield and cost issues.
2.3 Bandwidth Breakthrough Axis: UCIe Chiplets + CPO Optical I/O
As chiplet architecture spreads, scenarios combining chips from different companies are becoming reality. For example, to put Company A’s CPU chiplet, Company B’s AI accelerator chiplet, and Company C’s I/O chiplet in one package, all three chips must follow common interface specifications. That’s UCIe (Universal Chiplet Interconnect Express).
UCIe is a standard with participation from major industry players including Intel, AMD, TSMC, Samsung, ARM, and Google. UCIe 1.0 came out in 2022, with UCIe 2.0 in 2024 and UCIe 3.0 in 2025, continuously upgrading bandwidth and scalability. UCIe includes physical layer (PHY), die-to-die link protocols, and packaging guidelines.
UCIe’s core value is ecosystem expansion. Previously AMD only connected its own chiplets and Intel only its own tiles, but as UCIe matures, customers can directly combine “Intel CPU + AMD GPU + Marvell I/O.” This has potential to change the semiconductor industry structure itself. Of course, actualizing this requires solving ecosystem issues like IP licensing, testing, and security, but the technical foundation is already laid.
Meanwhile, I/O leaving packages is also a bottleneck. AI accelerators communicate with other accelerators through network switches, and switch bandwidth requirements are exploding. Traditional electrical signal-based SerDes faces serious power consumption and signal integrity issues beyond 50Gbps, 100Gbps.
CPO (Co-Packaged Optics) solves this with optical communication. Optical transceivers are attached inside or right next to packages, minimizing the distance for electrical-to-optical conversion. Previously optical modules plugged into QSFP cages tens of centimeters from switch ASICs—CPO reduces this distance to millimeters. Power efficiency greatly improves and higher bandwidth can be achieved.
CPO’s technical challenge is integrating optical engines with electronic chips. Silicon photonics technology can integrate optical waveguides and modulators on wafers, but yield and alignment accuracy are key. Also, where to place laser light sources and how to cool them remain homework. Nevertheless, because electrical I/O physical limits are clear, CPO seems an unavoidable direction.
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3. 2030 Outlook: Three Decisive Factors
Large-Scale and 3D Simultaneously
Semiconductor packaging will evolve in two directions: “larger” and “denser.”
Area expansion: AI chips continue growing. NVIDIA’s Rubin architecture is expected to require larger packages than existing Blackwell. Wafer-based CoWoS expansion continues, but ultra-large package demand partially shifts to panel level like CoPoS. If 2029 CoPoS mass production succeeds, panel level will become mainstream for large AI packages in the early 2030s. However, as Nomura reports noted, mass production timing might delay to 2029-2030.
Density maximization: 3D stacks spread to pack more functions in the same area. Hybrid bonding pitch drops below 3 micrometers based on Intel Foveros Direct gen-2. HBM can go beyond 16 layers to 20, 24 layers. Both SK hynix and Samsung are researching 16+ layer HBM stacks.
Hybrid structures placing multiple 3D stacks on large-area packages are natural. Area and density axes ultimately merge. TSMC already offers combinations placing SoIC on CoWoS. NVIDIA Rubin is also expected to combine CoWoS-L and SoIC. The same approach works at panel level.
Power Delivery and Substrate Innovation Determine Performance
Backside Power Delivery: Intel PowerVia was already applied in Arrow Lake and continues expanding in next-gen products. TSMC is known to introduce BSPDN (BackSide Power Delivery Network) in the A16 process (1.6nm-class). Moving power lines to the wafer backside leaves the frontside for signal lines only, increasing routing headroom and reducing IR drop (voltage drop).
As backside power becomes mainstream in 2026-2027, package power network design also changes. With power wiring on the backside, the backside can also be used for cooling. Extracting heat from both front and back sides can lower temperatures even in high-power-density chips. Combined with direct-to-chip liquid cooling, this becomes core technology for stably operating 1,200W+ AI packages.
Glass Substrate: Traditional organic substrates made from polymer materials like epoxy resin have large thermal expansion coefficients and limited flatness. Glass substrates excel in flatness with thermal expansion coefficients close to silicon. They provide 10x higher interconnect density and superior structural stability versus organic substrates.
Intel officially announced glass substrates for 2027-2029 market introduction and operates dedicated glass substrate facilities in Arizona. TSMC is also validating glass substrates in cooperation with Corning. Glass substrates solve warpage and wiring precision problems in ultra-large packages. Even hundreds-of-square-centimeter packages difficult with organic substrates become possible with glass.
RDL (Re-Distribution Layer) advancement: Redistribution layers core to CoWoS-R and fan-out packaging also evolve. Wiring pitch drops below 2 micrometers and multi-layering advances, simultaneously improving signal integrity and power efficiency. TSMC plans major RDL technology enhancements in CoWoS with 9.5x reticle size scheduled for 2027 mass production.
Packaging Becomes a Comprehensive Battle of Technology, Capacity, and Ecosystem
2030 semiconductor industry winners will have all three.
Technology: Not just cutting-edge processes but advanced packaging technologies. Must offer all options including 2.5D (CoWoS, EMIB), 3D (SoIC, Foveros, X-Cube), hybrid bonding, panel level (CoPoS), CPO, backside power, glass substrates to attract customers. This is why TSMC aims to provide CoWoS, SoIC, and CoPoS.
Capacity: Technology alone is useless without production capacity. TSMC dominates now because it secured CoWoS capacity faster than others. TSMC plans to reach 90,000-100,000 wafers monthly CoWoS capacity by end of 2026. Samsung and Intel are investing trillions in capacity expansion but haven’t caught TSMC yet.
Ecosystem: Not just making chips, but platforms unifying materials, equipment, OSATs, IP companies, and customers. TSMC’s OIP (Open Innovation Platform) and Intel Foundry Services both aim to secure ecosystems. Standards like UCIe are also ecosystem expansion tools. NVIDIA securing 50%+ of TSMC CoWoS capacity doesn’t just mean good technology—it means preempting TSMC’s entire ecosystem.
Technology alone, capacity alone, or customers alone aren’t enough. Platforms that can supply process, packaging, substrates, equipment, inspection, cooling, and optics as one bundle win.
4. Promising Semiconductor Packaging Companies: Where Value Is Created
Foundry War: Vertical Integration of Foundry and Packaging Technology
TSMC currently dominates advanced packaging markets. Based on overwhelming CoWoS share, NVIDIA alone secured 50%+ capacity. SoIC is already mass-producing, with CoPoS targeting 2029 mass production. TSMC’s strength isn’t just technology but capacity and ecosystem. TSMC is building advanced packaging facilities not just in Taiwan but in Kumamoto, Japan and Arizona, USA. End-2026 CoWoS monthly capacity is projected to reach 90,000-100,000 wafers.
Samsung Electronics has I-Cube 2.5D and X-Cube 3D packaging but lags TSMC in capacity and ecosystem. Samsung’s strength is vertical integration of both HBM and foundry. It can differentiate in logic+HBM integrated packaging, but short-term catch-up is difficult since TSMC already preempted the CoWoS market. Samsung targets 2026 X-Cube mass production.
Intel has the broadest technology portfolio with EMIB + Foveros + PowerVia + glass substrates. Backside power (PowerVia) was already applied in Arrow Lake, with glass substrates under development in dedicated Arizona facilities. Through Intel Foundry Services it aims to provide packaging to external customers, but customer acquisition is key. Intel challenges TSMC with a “process + packaging bundle” strategy combining 18A (1.8nm-class) process and advanced packaging.
OSAT Rise: From Simple Assembly to Core Partner
The AI era changed OSAT positions. Previously “foundries make chips, OSATs just assemble” was the perception, but in advanced packaging OSATs became core.
ASE Technology Holding is the world’s largest OSAT. Advanced packaging revenue increased 30%+ year-over-year from 2024-2025. ASE provides fan-out, 2.5D, and 3D stacking. Major customers include NVIDIA, AMD, Qualcomm, expanding dedicated advanced packaging lines in Taiwan and China. Over 40% of 2025 capex went to advanced packaging.
Amkor Technology broke ground on an Arizona advanced packaging campus with total investment exceeding $2 billion. Slated for 2027 operation, it received $400 million+ in CHIPS Act funding in 2024. NVIDIA collaboration was disclosed, with particular strength in HBM packaging. Also closely cooperating with SK hynix.
JCET Group is China’s largest OSAT. Despite US-China tech competition, it’s accelerating AI and advanced packaging investment. Expanded fan-out and 2.5D packaging lines in 2024-2025. As China’s domestic AI chip demand grows, JCET’s growth potential can’t be ignored.
HBM Manufacturers Enter Packaging
No AI chips without HBM, no finished products without packaging connecting HBM to logic. So HBM manufacturers are strengthening packaging capabilities.
SK hynix is #1 in HBM market share. Estimated 50%+ HBM market share as of 2024. Started HBM3E 12-layer mass production in 2024, unveiled 16-layer HBM4 samples in November 2025. Targeting H1 2027 mass production. Established advanced packaging R&D center in Indiana, USA, expanding cooperation with Amkor. If SK hynix further builds packaging capabilities, it could make logic+HBM finished products directly without TSMC dependency.
Samsung Electronics started HBM3E mass production in H2 2024, rapidly increasing supply in 2025. Samsung is the only company with memory, foundry, and packaging. Samsung Electro-Mechanics is #1 in FC-BGA substrate market share, supplying substrates for products like NVIDIA H100, H200, Blackwell GB200. FC-BGA revenue grew 30%+ year-over-year in 2024. Samsung’s challenge is bringing foundry and packaging capacity to TSMC levels.
Micron Technology is #3 in HBM market. In 2025 Singapore investment announcement, Micron mentioned its HBM advanced packaging plant could contribute to supply from 2027. Plans to invest ~$7 billion in Singapore advanced packaging facilities.
CPO and Networking Silicon
Broadcom most aggressively pursues CPO. The Tomahawk 6 switch announced in December 2025 applies 3rd-gen CPO technology based on 200Gbps per lane. Improves power efficiency 40%+ versus electrical SerDes while providing total 25.6Tbps bandwidth. Slated for 2026-2027 mass production, already cooperating with hyperscalers like Google, Meta, AWS, Microsoft. Broadcom’s CPO will first apply to networking switches short-term but is expected to expand to GPUs and AI accelerators mid-to-long term.
Marvell Technology is also investing in datacenter networking and silicon photonics. Marvell is developing solutions combining PAM4 DSP (Digital Signal Processing) and optical interconnect technology.
POET Technologies attacks the CPO market with a unique platform called Optical Interposer. Traditional interposers connect electronic chips with metal wiring—POET integrates optical devices like waveguides, lasers, and filters inside the interposer. Fully CMOS-compatible and wafer-scale manufacturable, significantly reducing cost versus traditional optical modules.
Ayar Labs and Lightmatter startups are also developing intra-chip optical interconnect technology. They aim to pull the electrical-to-optical conversion point deeper inside chips, targeting optical conversion even for die-to-die connections inside GPUs.
The CPO market’s turning point is 2026-2027—when companies transitioning from pilot to mass production are decided and hyperscalers begin large-scale adoption.
Conclusion
Post-2026 AI semiconductor competition has shifted focus from “who makes better dies” to “who can assemble and ship systems faster, larger, and more reliably.”
Process scaling remains important, but that performance can’t become systems without packaging. This is why NVIDIA CEO Jensen Huang said in 2024 earnings calls “advanced packaging capacity quadrupled over two years yet remains a bottleneck.” Even making HBM and fabricating logic dies in cutting-edge processes, products can’t ship without 2.5D assembly slots.
The next 3-5 years will be the packaging war era. Winners are determined by who makes larger packages (CoPoS), stacks denser (hybrid bonding), connects faster (UCIe, CPO), and cools more efficiently (microfluidic, backside power).
Winners will be platforms with technology, capacity, and ecosystems. TSMC currently leads, but Intel’s glass substrates and backside power, Samsung’s HBM+foundry vertical integration could be wildcards. Korean companies have strengths in HBM and substrates, but without controlling entire packaging platforms must cede much value-add to TSMC.
Ultimately, the 2030 semiconductor industry landscape will be determined by “who controls packaging ecosystems.”
2026 pilot lines for CoPoS show TSMC is committing capital before yield data exists. That timing, not the 2028 target, is what matters.